About CS1 on Port A of QuadSPI configuration parameters

[goto11]

Hello,

I am using QSPI_A to access memory.
Since the QSPI_A_SS0_B and QSPI_A_SS1_B signals are Chip select1 port0/1 deviceA, shouldn't CS1 on Port A be set to enable?
The designer says that CS1 on Port A can be accessed with the disable setting.
Is there any problem with this setting?

Regards,

Goto

[Yuri]

@goto11 
Hello,

   QSPI_A_SS0_B may be used without QSPI_A_SS1_B.
Section 10.2.8.2 (Dual Die Flashes) of i.MX 7Dual Reference
Manual (Rev. 1, 01/2018) describes configuration, where
both signals are applied.

Regards,
Yuri.

[goto11]

Hello,

It's not the answer to what I asked.
Is the QSPI_A_SS0_B(QSPI_A_SS1_B) signal valid when the CS1 on Port A setting in Table 6-50 (QuadSPI configuration parameters) is disabled?

Regards,

Goto

[Yuri]

@goto11 

  The QSPI_A_SS0_B signal is valid when the CS1 on Port A setting in QuadSPI configuration parameters is disabled. QSPI_A_SS1_B is not configured for QSPI in such case.

~Yuri.

[goto11]

Hello,

When the setting value of "CS1 on Port A" in Table 6-50 (QuadSPI configuration parameters) is disabled, is it not possible to use Flash A2 with the following configuration?

 

Regards,

Goto

[Yuri]

@goto11 

 if "CS1 on Port A" in  QuadSPI configuration parameters is disabled, 
it is not possible to use the Flash A2.

[goto11]

If the setting value of "CS1 on Port A" in Table 6-50 (QuadSPI configuration parameters) is enable, can Flash A2 with the following configuration be used?

[Yuri · Accepted solution]

@goto11 

  yes.