what is the bandwidth between the A5 and the M4

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what is the bandwidth between the A5 and the M4

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Contributor I

Hi

I'm trying to get a fell for the maximum data rate from the M4 processor in the Vybrid to the A5.  Ballpark figures would be fine.

i.e. is that 10K,100K, 1M Bytes/sec ?

Thanks,

Andrew

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Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

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Contributor I

Jiri Do you have an update on this? 7MB/sec is unacceptably low. I would be curious what is the current speed now.

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NXP Employee
NXP Employee

Hello KTC,

do not have any update. This was example of one use case which included copying, sema4 locking and interrupt handling. Theoretical bandwidth is much fast (see above). Without double copying and different interrupt handling you can achieve much better results for your use case.

/Jiri

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NXP Employee
NXP Employee

Hello Andrew,

The communication between Cortex-A5 and Cortex-M4 is usually performed via shared memory. Usually it is internal SRAM2 (256kB) protected via HW semaphores.

From HW point of vie we can compute like this:

64 bit wide AXI bus

133 - 166 MHz clock

Test use case (more about architecture in AN4947):

  • Cortex-M4 write to the memory 4 clock, 4 clock accept by memory
  • Read from memory by Cortex-A5 8 clocks, 4 clocks read accept
  • the transfer itself takes about 20 NIC clocks
  • theoretical bandwidth at beginning of communication is 8B (64b) * 166 MHz / 20 cycles = 66.4 MB/s

  • Every following transfer can be done in one cycle write + one write cycle read (up to 32 bytes)
  • so theoretical bandwidth then is 8B (64b) * 166 MHz / 2 = 664 MB/s
  • this can be achieved when caches or DMA is used only.

Final communication speed depends on how the communication is implemented. Usually transmitter have to lock the semaphore, write into the memory, unlock the semaphore, raise CPUtoCPU interrupt to inform the receiver (the other core) that data are ready. Receiver has to proceed interrupt, lock .....

So It depends on operating system or drivers that you use.

/Jiri

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NXP Employee
NXP Employee

Hello Andrew,

one use case test result:

MQX on Cortex-M4 to MQX on Cortex-A5:

- M4 has data ready in its buffer

- M4 copy 1kB data into mcc buffer

- A5 copy 1kB into its buffer

it took 136us (time includes copying, semaphores locking, interrupt handling on both sides)

-> about 7MB/s

Tested on debug target (release will be faster). We can also expect little bit lower transfer rate in Linux x MQX and little bit higher in baremetal applications.

/Jiri

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