do not have any update. This was example of one use case which included copying, sema4 locking and interrupt handling. Theoretical bandwidth is much fast (see above). Without double copying and different interrupt handling you can achieve much better results for your use case.
The communication between Cortex-A5 and Cortex-M4 is usually performed via shared memory. Usually it is internal SRAM2 (256kB) protected via HW semaphores.
From HW point of vie we can compute like this:
64 bit wide AXI bus
133 - 166 MHz clock
Test use case (more about architecture in AN4947):
Final communication speed depends on how the communication is implemented. Usually transmitter have to lock the semaphore, write into the memory, unlock the semaphore, raise CPUtoCPU interrupt to inform the receiver (the other core) that data are ready. Receiver has to proceed interrupt, lock .....
So It depends on operating system or drivers that you use.
one use case test result:
MQX on Cortex-M4 to MQX on Cortex-A5:
- M4 has data ready in its buffer
- M4 copy 1kB data into mcc buffer
- A5 copy 1kB into its buffer
it took 136us (time includes copying, semaphores locking, interrupt handling on both sides)
-> about 7MB/s
Tested on debug target (release will be faster). We can also expect little bit lower transfer rate in Linux x MQX and little bit higher in baremetal applications.