how to disable cache, ESDHC card

[MehmetAliIpin]

Hello,

I could finally download my application into our prototype board's QSPI XIP flashes, and started debugging the code with DS-5. During debug, I saw that boot  code is enabling/disabling cache. And also checking the ESDHC. But we are using VF3x processor, which has no chache in it. Also we don't have SD card in our prototype.

How can I disable these peripherals? in user_config.h?

thanks and best regards.

Mehmet Ali Ipin

[timesyssupport]

Hi Mehmet,

Are you looking to disable ESDHC/cache in MQX, Linux, or both? With MQX, you should be able to disable ESDHC in user_config.h. With Linux, the latest kernel checks to see if L2 cache is present before attempting to use it. L2 cache can otherwise be disabled in the kernel configuration. ESDHC support can be disabled in the board definition file, at arch/arm/mach-mvf/board-twr-vf700.c in the Linux source tree.

Thanks, and let me know if you have any questions.

Timesys Support

[MehmetAliIpin]

Hi,

I am looking to disable both ESDHC and cache in MQX.

I guess I should re-set the (#define BSPCFG_ENABLE_ESDHC      1)  to zero;

I only find letter "cache" in line

#define MQX_USE_UNCACHED_MEM     1

Is it this to disable cash, or  are there other lines?

Thanks and best regards.

Mehmet Ali Ipin

[timesyssupport · Accepted solution]

Hi Mehmet,

Setting MQX_USE_UNCACHED_MEM to 1 will make MQX compile in support for uncached memory allocation. I also found some cache-related settings at mqx/source/psp/cortex_a/vybrid.h, lines 73-109 (this is for running MQX on either the A5 or M4 core).

Thanks,

Timesys Support

[MehmetAliIpin]

Dear Timesys,

I know VF3x has no L2 cache, but in ref manual table 2-4, I read A5 has L1 cache, does it mean data and code caches are available in VF3x? In this case I should only close L2 cache is that true?

#define PSP_HAS_L2_CACHE            0

Thanks and best regards

[timesyssupport]

Hi Mehmet,

If you are running MQX on the A5 core, then the L1 and L2 cache will be enabled by default, according to mqx/source/psp/cortex_a/vybrid.h, lines 78-84. I am unsure if these are directly related to data/code cache, but changing any of the cache-related macros to 0 in vybrid.h will disable their functionality.

Thanks,

Timesys Support

[karina_valencia]

timesyssupport can you attend this case?