Hi Sugiyama-san,
The RD_DL_SET field is the amount of clock cycles that the PHY waits after it sends the Read Command to the DDR plus the Read Latency value, before it notifies the controller that data is read in the READ FIFOs to be passed to the controller. Stated another way: After the programmed number Read Latency clocks, the DDR will strobe out the first data byte on the data lane. The PHY will begin counting from that point the number of clock cycles programmed into RD_DL_SET, and then notify the controller that data in the READ FIFOs is valid.
The setting of RD_DL_SET accounts for all timing necessary to:
1) Transfer data from the DDR to the processor over the PCB,
2) Transfer data from the pins of the processor to the input of the READ FIFO.
3) The one-quarter clock phase shift of the DQS strobe to clock the DQ values into the FIFO
4) And any timing difference between the Controller clock domain and the PHY domain.
Also note that the controller is sent the data from both the rising edge and falling edge of the DQS strobe at the same time, and that data is transferred across the DFI bridge only on the rising edge of the master clock.
On most boards, a setting of 0x4 is all that is required. On PCB with much longer PCB traces, a setting of 0x5 may be neccessary to avoid problems. We currently recommend 0x5 as a settings just to keep customers from complaining. The net effect of adding clock cycles to RD_DL_SET is just adding latency to a Read operation, thus reducing throughput.
Hope this answers your question for you,
Mark
