Secure JTAG and reset: Vybrid stuck

[helmut_erich]

We are trying to get secure JTAG running on our devices with a Vybrid VF6xx. Establishing the connection, software download via Segger JFlash and issuing JTAG commands (halt, go etc.) via Segger JLink works as expected.

However, if the device is reset during the secure JTAG connection (via JTAG command or via SW reset), the device does not reboot properly. The device does the reset but then gets stuck with the PC somewhere around 0x6d54. As this address is before the starting address of our bootloader I assume it is part of the internal boot ROM.

The behavior is the same, if the JTAG connection is closed prior the reset. The only way to reboot the device again is a power cycle.

Is there a security feature that could prevent the device from booting properly after a reset occurred during or after a secure JTAG connection?

If so, can the device be configured to boot properly in such cases?

The E-Fuses for JTAG are set as follows:

* JTAG_SMODE 0x01 (secure JTAG)

* SEC_CONFIG 0x01

Thanks and best regards

[helmut_erich]

Thanks for your answer. We are using the software reset (SW_RST in SRC_SCR) for self-resets of the device and to recover from severe errors. Therefore a POR is not practicable in this case.

As I mentioned does the reboot after a software reset not work if a secure JTAG connection was established beforehand. If no secure JTAG connection was established it works without any problem. As the device does not even enter our bootloader there is no way to debug this.

So my question is does the JTAG_SMODE fuse or the state of the JTAG controller (SJC) influence the high assurance boot in any way? (The Vybrid F Reference manual stats that the JTAG controller is not reset during JTAG or watchdog resets)

Or could there be another issue that prevents the device from loading a bootloader after software reset?

[Yuri]

Hello,

  Please create request / ticket to get boot utility for boot crash analyzing.

Sales and Support|NXP 

Regards,

Yuri.

[Yuri]

Hello,

  It is recommended to remove power (voltage source) to all components on the board in the event

of a processor reset. This avoids having to determine if a component critical to rebooting the processor is in
the necessary state to support a reboot. So, the POR may be recommended for reboot.

Also, "any reset after JTAG access authorization will shift the JTAG controller

back to its lock state, requiring that this authentication process be repeated."

Have a great day,
Yuri

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