Vybrid DDR memory addressing

[sugiyamatoshihi]

Hello,

I'd like to know DDR memory addressing of Vybrid, because we have to check memory contents is correct or not.

I saw the DDr memory addressing map like below.

Does this means when data write/read to memory, address move to Column=>Bank=>Row.

So, data write/read column[0:9]->1k/bank0, then change bank 0 to 1 and column0-1k/bank1 after bank 7, then row0->1.

Is this correct?

I suppose sequential access means Column=>Row=>Bank, but Vybrid seems different.

Best Regards,

Sugiyama 

[Yuri]

Hello,

  DRAM address mapping for Vybrid is correct. You may also look at

section 10.1.6.1 (Address Mapping) of VFxxx Controller Reference Manual,

Rev. 0, 10/2016.

Have a great day,
Yuri

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