Using ECC with DDR3 in u-boot on Vybrid?

[sanchayanmaity]

Hello,

The Vybrid datasheet mentions ECC support with DDR3 in 8 bit mode. Currently trying to test this on Colibri Vybrid VF61 module with u-boot 2015.04-rc4.

The code snippet for enabling this ECC support is as below:

/* Clear ECC errors in IN_STAT DDRMC_CR80 */

    writel(0x00000078, &ddrmr->cr[81]);

/* Re-configure the DDR controller for an 8-bit port width; reduc = 1 */

    writel(0x0000010C, &ddrmr->cr[78]);

    /* Enable ECC - reporting and correcting on */

    writel(0x03000000, &ddrmr->cr[57]);

/* Need to disable checking on partial writes */

    writel(0x01000000, &ddrmr->cr[58]);

    ddrmc_phy_init();

    writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);

    while (!(readl(&ddrmr->cr[80]) && 0x100))

udelay(10);

    for (ptr = PHYS_SDRAM; ptr < (PHYS_SDRAM + 134217728UL); ptr++) {

*ptr = 0;

    }

/* Allow the ECC codes for the entire user word to be corrupted */

    writel(0x00000000, &ddrmr->cr[58]);

    int_stat = readl(&ddrmr->cr[80]);

    printf("INT_STAT: %x\n", int_stat);

This is base on what I understand from the section 34.6.5 of the Vybrid TRM and the register descriptions of CR57, CR58 and CR78. Currently, with this change in place u-boot hangs. To be more exact, it hangs in the relocate_code function, defined in arch/arm/lib/relocate.S. This is confirmed by having a debug print function call,

ENTRY(relocate_code)

    ldr    r1, =__image_copy_start    /* r1 <- SRC &__image_copy_start */

    subs    r4, r0, r1                /* r4 <- relocation offset */

    beq    relocate_done        /* skip relocation */

    ldr    r2, =__image_copy_end    /* r2 <- SRC &__image_copy_end */

copy_loop:

    b print_debug

    ldmia    r1!, {r10-r11}        /* copy from source address [r1]    */

    stmia    r0!, {r10-r11}        /* copy to   target address [r0]    */

    b print_debug

    cmp    r1, r2            /* until source end address [r2]    */

    blo    copy_loop

u-boot hangs at the ldmia instruction, so just before the relocation operation it hangs at that instruction with only the first debug print getting printed on the console and no second debug print. If ECC is disabled, it boots up.

Has this been tested on Vybrid with uboot by anyone? Any pointers?

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[sanchayanmaity]

Hello,

Anyone from Freescale can provide any inputs?

I came across this post

https://community.freescale.com/thread/318406

From what I can see atleast my configuration seems to be possibly correct as per the replies by jiri-b36968.

Thanks & Regards,

Sanchayan Maity.

[karina_valencia]

timesyssupport  are you able to check this case?

[timesyssupport]

Hello Karina,

At this time, we are not in posession of Toradex Vybrid hardware, and the U-boot version is beyond our current supported releases. Perhaps a Toradex engineer will be able to assist?

Thank you,

Timesys Support

[sanchayanmaity]

Hello,

I am from Toradex itself and have been working on this.

I do not think u-boot version will make much difference thereof. The Colibri Vybrid support is also based off on the Vybrid tower as such and though we change some settings for DDR (3 parameters to be exact), much of stuff is quite similar. The patchset for adding support is also not that big and we have had 2014.04, 2014.10 and 2015.04-rc5 now.

In case you want to look at the patchset which we recently submitted and is under review, can be found here

https://www.mail-archive.com/u-boot@lists.denx.de/msg167419.html

I did be interested if someone from Timesys or otherwise can confirm this with whichever u-boot version they support and if ECC works for them with which settings.

As such the ECC documentation does not say much in the reference manual.

Regards,

Sanchayan.

[timesyssupport]

Hello karinavalencia and sanchayanmaity,

Please pardon the delay, we have not validated ECC DDR RAM, currently we are not in posession of Vybrid hardware using ECC RAM.

Thank you,

Timesys Support

[sanchayanmaity]

Hello,

Is ECC really a function of the DDR in this case?. From my understanding, it is related to the Vybrid's DDR memory controller and not tied to the DDR being used. Am I wrong in my understanding?

To reiterate and also as stated on the below link by Francois Juillet which neither Naoum Gitnik nor Jiri stated as wrong

https://community.freescale.com/thread/318406

"The ECC is a functionality of SDRAM memory controller. Tthe DDR3  memory chip is used for stocking syndrom and not for compute ECC. When we activate the ECC , we need to 10 bit in memory for stocking the ECC (8 bit user data + 2 bit ECC) so we need to reduce the datapath to 8 bit for stocking 2 ECC bits. If we keep memory datapath to 16 bit, there is no place to store 2 bits of ECC. So DDR3 chip does not need ECC functionality because it is memory controller which integrates this functionality".

Thanks & Regards,

Sanchayan Maity.

[karina_valencia]

jiri-b36968 can you comment please?

[jiri-b36968]

Hello,

ECC for SDRAM is feature of the controller. When ECC is enabled the SDRAM memory has to be initiated. Check codes are computed by the controller and stored in SDRAM memory. For each 32-bit word is generated 7-bit check code. When ECC is enabled data bus width decreases from 16 bit to 8 bit. 8 data bits + 2 bits ECC. This is also main reason why default for reference design is non-ECC configuration - bandwidth is half in ECC mode. There is no plan to support it by Freescale in SDK - Timesys could do it, but as Timesys said there is no plan for it now. On other hand it is not complicated to enable ECC on DDR (done quick test long time ago  Re: Re: Re: how to enable ECC on OCRAM and DDR3 with TWR-VF65GS10 board; Re: Re: Re: how to enable ECC on OCRAM and DDR3 with TWR-VF65GS10 boardRe: how to enable ECC on OCRAM and DDR3 with TWR-VF65GS10 board.)

/Jiri

[timesyssupport]

Hello sanchayanmaity,

Our Vybrid maintainers will review, and we will follow up once we've had a chance to do so.

Thank you,

Timesys Support

[karina_valencia]

timesyssupport do you have an update?