Dear,
I am designing Board with Vybrid VF6 and I have doubt about SDHC layout recommentaions appears in paragraph 3.3.2.3 SD Card interface requirements of ref. doc. VYBRIDHDUG_HW_UserGuide.
In this paragrap appears:
1. The clock trace should be longer than the longest trace in the Data /Command group (+5mils).
Is 5mils minimun distance or maximum ?
2. SD card interface layout requirements are very similar to those for the DDR one (see Section 3.5,
“DDR routing rules”).
But in this section appears DDR3 recommnedations?
I need to kown routing recomentadion to SDHC.
Can somebody help me?
Thank you in advance.
Solved! Go to Solution.
jiri-b36968 can you comment please?
Hello Fernando,
yes, reference design uses DRAM memory type DDR3 (DDR is imprecise expression).
SDHC runs up to 50MHz.
- try to make lines short
- match all lines length.
- Add 5 mils to clk.
- try to keep lines on one layer.
- Ensure correct return path (continuous ground under lines)
- consider ESD protection if SD card is accessible to users.
/Jiri
Thank you
Hi Karina valencia Aguilar,
Can the NXP Vybrid Hardware team please comment on this?
Thanks
Timesys Support