L2 cache, TCM enable

cancel
Showing results for 
Search instead for 
Did you mean: 

L2 cache, TCM enable

Jump to solution
1,220 Views
Contributor III


Hi,

I am using TWR-VF65GS10, I want to check whether L2 cache is enabled or not,

I found BT_MMU_DISABLE and L2_CACHE_DISABLE in reference manual, but I don't actually know how and where to use it.

And I also want to check whether TCM is enabled or not, how can I do that?

Thanks,

Labels (5)
0 Kudos
1 Solution
150 Views
Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

View solution in original post

0 Kudos
4 Replies
151 Views
Community Manager
This an automatic process.

We are marking this post as solved, due to the either low activity or any reply marked as correct.

If you have additional questions, please create a new post and reference to this closed post.

NXP Community!

View solution in original post

0 Kudos
151 Views
Senior Contributor II

Hi,

>  I am using TWR-VF65GS10, I want to check whether L2 cache is enabled or not,
>  I found BT_MMU_DISABLE and L2_CACHE_DISABLE in reference manual, but I don't actually know how and where to use it.

To check whether you have L2 cache, see the digit before N letter in part number. 1N indicates that you have L2 cache and no RAM, 0N indicates that no L2 cache but 0.5MB RAM. It seems by default MMU, L1 Data and L2 caches of the Cortex-A5 core are enabled by boot loader.

Refer this thread for Enable/Disable L2 cache using register. https://community.nxp.com/thread/330937.

>   And I also want to check whether TCM is enabled or not, how can I do that?
TCM is standard SRAM memory which is connected directly to Cortex-M4 via local memory
controller.I believe this is seleted by default.

Thanks
Timesys support.

151 Views
Senior Contributor II

Hi,

In order to enable the M4 core in code please follow this steps.

1) SRC->GPR[2] = <start address> + 1; //since M4 is thumb

2) CCM->CCOWR = 0x15a5a; //Start secondary core

To know more about starting the M4 core please follow this thread.

https://community.nxp.com/thread/306741

Thanks

Timesys Support

151 Views
NXP Apps Support
NXP Apps Support

timesyssupport​ can you help here?

0 Kudos