Hi
I am working on PARALLEL QSPI for Vybrid Custom Board and currently unable to boot the board (When image was flashed for non-parallel mode, Boot is successful) Here is my QSPI configuration
const SFLASH_CONFIGURATION_PARAM quadspi_conf __attribute__ ((section ("conf")))= {
0, /* Reserved 0 */
0, /* Hold Delay for QSPI[0,1] A/B */
0, /* Select sampling at non-inverted clock */
0, /* One Clock cycle delay */
0, /* Reserved 1 */
{0, /* Reserved 2 */
0, /* Reserved 3 */
0}, /* Reserved 4 */
0, /* cs_hold_time */
0, /* cs_setup_time */
0x1000000, /* A1 flash size - 16MB (This is not a dual die flash) */
0, /* A2 flash size (This is not a dual die flash) */
0x1000000, /* B1 flash size - 16MB` (This is not a dual die flash) */
0, /* B2 flash size (This is not a dual die flash) */
3, /* SCLK Frequency (0-18MHz, 1-60MHz, 2-74MHz, 3-104 MHz (SDR Mode) ) */
0, /* Reserved 5*/
4, /* Quad Mode Flash (4-bit) */
1, /* Port A is always available. This field informs the device ROM the availability of Port B. 0 - Port B is not used. 1 - Port B is used */
0, /* Dual Data Rate (DDR) Mode Disable */
0, /* Data Strobe signal (DQS) Disable */
1, /* Parallel Mode Disable (This field enables the device ROM to configure the QSPI interface
in parallel mode. Data will be read from serial Flash in parallel mode. ) */
0, /* Disable Port A CS1 */
0, /* Disable Port B CS1 */
0, /* FS Phase (Select sampling at non-inverted clock) */
0, /* FS Delay (One clock cycle delay) */
0, /* DDR Sampling (Select the sampling point for incoming data when serial flash is in DDR mode) */
/* LUT Programming */
/* Quad read*/
{0x04EB, /* Instruction - (CMD-1) || 1 - Pads || QIOR - Quad IO Read (3 or 4-byte address) */
0x0A18, /* Instruction - (ADDR-2) || 4 - Pads || 24 bit address */
0x12A5, /* Instruction - (MODE-4) || 4 - Pads || Remain in QIOR */
0x0E04, /* Instruction - (DUMMY-3) || 4 - Pads || 4 Dummy Cycles */
0x1E80, /* Instruction - (READ-7) || 4 - Pads || 128 Bytes */
0x2401} /* Instruction - (JMP_ON_CS-9) || 1 - Pads || to 1 */
};
Is these settings correct?
In my programme of flashing the binary image, I have adapted the following scheme.
#define HEADER_SIZE 2048 // Also checked for 512
1. Split the original image (total_image_size-HEADER_SIZE) into "d1" and "d2" arrays
2. Copy Boot Configuration Header of "HEADER_SIZE" Bytes [1024 + 32 + 16 + 976 i.e. conf + IVT + boot_data_qspi + DCD] into "h_d" array from original image
3. Copy the "d1" array into "h_d" (after header). Now "h_d" contains Boot Configuration Header of "HEADER_SIZE" Bytes and then "d1" array
4. Flash "h_d" into Flash A
5. Flash "d2" into Flash B (start at HEADER_SIZE of Flash i.e. 0x21000800)
6. Set the Quad Bit to 1 in Flash Configuration Register 1 which is non-volatile bit.
7. Invalidate the TX and RX buffers (bits 10 and 11)
8. Set Parallel mode bit (Bit 16 of BFGENCR register)
where
I have barrowed split.c file. Is code provided in split.c considering quad mode bit settings?
Note:
1. The chip in use is Spansion FL128SAIF00 (SDR not DDR)
2. In Freescale "Document Number: TWRVF65GS10UG Rev. 1.2, 08/2014 Section 2.8", It is written that "QuadSPI interface supports Parallel QuadSPI operation in DDR mode." My chip is SDR so can I claim that "QuadSPI interface does not supports Parallel QuadSPI operation in SDR mode."
Regards
