I'm using a Vybrid processor (A5 + M4). I need to pass data from the M4 to the A5 core in DDR memory. I can't simply write to a memory space using the M4 and have the A5 read the same space because the A5 data is cached. The A5 would know nothing about the new data. Is there a way to accomplish this?
Since there has been no real answer to this question, I have to assume that there is no reasonable way for the A5 core and M4 cores to talk to each other short of going through some peripheral (such as a UART or SPI port). Sad that no form of non-cached common memory was designed in.
Look into MCC (MultiCore Communication). If you are using Linux on the A5, there is a driver for that. If you are using MQX on the M4, there is a library for that, too.
MCC, out of the box, doesn't use DDR. It uses part of the on-chip dual-port memory. If you want to use DDR, you'll have to modify the sources for that on both sides.
I looked through the Vybrid Reference manual (V9) and the MQX RM (V 19 MQX V 4.02) and neither has any mention of dual-ported memory or MCC. Is the dual-ported memory made up using software, or is there an actual hardware dual-port memory hidden somewhere?