High-level input higher than ovdd

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High-level input higher than ovdd

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Contributor II

Dear Sir or Madam:

we are evaluating multiple options to power the Vybrid using a single 3.3V supply. We are looking into a 1.5V-controlled LDO as the sequencing device shown in the block diagram attached. However, we have some concerns about the Vybrid. Could you please comment on our questions below?

  1. We realize that there will be a little dropout voltage between 3.3V_P and 3.3V_S anyway. In our application, 3.3V_S will power the  Vybrid and 3.3V_P will power some peripheral digital electronics around it. It is possible that a logic-high input (powered by 3.3V_P) is higher than 3.3V_S that powers the Vybrid GPIO. The data sheet says that the high-level input has a max. value of ovdd, which is 3.3V_S in our case. Will a “higher-than-3.3V_S” cause any damage or malfunctions? What do you think?
  2. In the configuration shown in the block diagram, peripheral electronics will be powered on before the Vybrid (3.3V_P turns on before 3.3V_S). In case there are high-level inputs at some GPIO pins before 3.3V_S is on, we guess these inputs will be shunted to the internal 3.3V rail by the internal protection Schottky diodes. If this is true, the Vybrid 3.3V rail is virtually powered by the high-level input minus the voltage drop on the Schottky diodes. Will this phenomenon cause the Vybrid to enter a “partially-powered” state and malfunction?

Please kindly let us know what you think.

Thanks and regards,

Shoumin

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NXP TechSupport
NXP TechSupport

Q. Will a “higher-than-3.3V_S” cause any damage or malfunctions?

A. Yes, it can cause an excessive input current and even I/O buffer damage.

Q. Will this phenomenon cause the Vybrid to enter a “partially-powered” state and malfunction?

A. Yes, this can cause a malfunction. The general requirement is that no I/O pins must be externally driven until the processor is powered on.


Have a great day,
Artur

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