About movement of DDRMC after having returned from LPSTOP3

[soichiyamamoto]

Hi,

After LPSTOP3 exit, I set DDRMC again.

And I set it with DDRMC_CR00=0x0501.

Then there is the case that DDRMC_CR80[bit8] is not set.

I set it in CCM_CCSR=01, and outbreak frequency increases when I enter LPSTOP3.

Q1）

When DDRMC_CR80[bit8] is not set, what will be regarded as a factor?

Best regards,

soichi

[naoumgitnik]

Dear Soichi,

There have been several threads about entering/existing LPStop modes, quite detailed , even with working code samples attached:

1. Have you tried using working code from there?
2. How is your current use case different than those in the above-mentioned threads, please, that it is causing some issues?

Sincerely, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

Thank you for reply.

1.Yes

2.No.

Best Regards,

soichi

[naoumgitnik]

Dear Shigenobu Katagiri,

As the LPStop entry/exit code author, may you comment on Yamamoto-san's request, please?

Thanks in advance, Naoum Gitnik.

[shigenobukatagi]

As far as I know, CR80 bit 8 which means completion of DRAM initialization needs stable clock for DDRMC.

Therefore 24MHz XTAL input to PLL path should be validated on customer's board.

I heard Yamamoto-san's customer has already confirmed it, and fixed this issue once by adjusting 24MHz input.

Yamamoto-san,

could you please share us more detail?

Best Regards,

Shigenobu Katagiri

[soichiyamamoto]

Dear Katagiri-san, Naoum-san,

Thank you for relry.

This issue is not completely fixed.

It is considerably little outbreak frequency.
Therefore,My and my customer investigated a factor of issue.

As a result, the situation changes by setting of ANADIG_PLL2_PFD[PFD2_FRAC].

I do adjusting 24MHz input.And DDRMC use PLL2 PFD2.

Frequency rises when I set ANADIG_PLL2_PFD[PFD2_FRAC]＝0x35. And  PFD2_STABLE is 1.

But,The problem does not occur when I set ANADIG_PLL2_PFD[PFD2_FRAC]＝0x34.

Q1)Is the setting of ANADIG_PLL2_PFD[PFD2_FRAC] = 0x35 NG?

Q2)Please comment.

Best regards,

soichi

[naoumgitnik]

Dear Shigenobu Katagiri,

May you comment on the above, please?

If required, feel free to communicate with Yamamoto-san off-line and just place the results/conclusions in this thread.

Thanks, Naoum Gitnik.

[soichiyamamoto]

I did talks in local.

I may be due to an outside 24MHz oscillation.

I must investigate a more concrete cause.

Therefore this Thread closes it once.

Best regards,

soichi