About LPSTOP3 mode and VREG_CTRL

[soichiyamamoto]

Hi,

I want to reduce current consumption in a standby mode(LPSTOP3 mode).

Therefore I set FIRC OFF out of LPSTOP3.

case 1:

I tested follows. And system reset occurred when I returned from LPSTOP3.

　VREG_CTRL＝0x01

　FIRC、FOSC、SOSC＝OFF。

　SIRC＝ON。

　CCM_CCSR[SYS_CLK_SEL]=0x01

　A mode changes to LPSTOP3.

case 2:

I tested follows. And I succeed in return from LPSTOP3.

VREG_CTRL＝0x03.

FIRC、FOSC、SOSC=off.

SIRC＝on.

CCM_CCSR[SYS_CLK_SEL]=0x01.

A mode changes to LPSTOP3.

I ask about this problem.

The difference between ”case1” and ”case2”is "VREG_CTRL = 0x01" and" VREG_CTRL = 0x03".

From a reference manual, the first bit of VREG_CTRL is Reserved bit.

From the test mentioned above, I think like a bit with a special function.

Q1)Please tell me about a special function of this bit in detail.

Q2)Please tell me the function when I made this bit clear.

Q3)Please tell me the function when I made this bit set.

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

In general, touching reserved bits is not recommended - “Reading/writing to reserved bits may result in unknown behavior”. Very often such bits control the processor's behavior, and their default values are optimal for its operation. Your case is an example thereof; without going into the confidential design details, the bit of interest is indeed related to the LPStop mode entry/exit, and its default / "Reset" (i.e. optimal) value is "1".

Thus, the problem does not go away by writing 0x03 to VREG_CTRL but actually it is created by first writing 0x01 to the register, thereby making VREG_CTRL[1] bit 0.

My understanding of why you decided to consider the "0" value for this bit is that in the Reference Manual the "R" (Read) value for this bit is "0", which is a bit confusing... The point here is that in fact the value is "1" (and should not be changed!) but this bit is of a special,  so-called "disabled for read" kind, which always returns "0" regardless of the actual value.

Sincerely, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

Thank you for reply.

Please tell me the association of VREG_CTRL[1] bit 0 and LPStop mode in detail.More concrete content.

Best Regards,

soichi

[naoumgitnik]

Dear Soichi,

The maximum we can disclose is that bit is involved in controlling power for the LPStop mode (which just confirms what you already know based on your own observations).

Regards, Naoum Gitnik.

[soichiyamamoto]

Dear Naoum,

When I set 1 in VREG_CTRL[1] bit, VREG_CTRL[1] bit is readable to 1.

And VREG_CTRL[1] bit is readable to 0 when I set 0 in VREG_CTRL[1] bit.

This is the reality.

Thus,I think that there is not VREG_CTRL[1] bit in Read Only.

As for this bit, is 1 right?

Best Regards,

soichi

[naoumgitnik · Accepted solution]

Dear Soichi,

Briefly, yes, the "1” value is correct and shall never be changed.

Regards, Naoum Gitnik.

[naoumgitnik]

Dear Soichi,

I will verify that bit's function with the Vybrid IC design team; please, expect reply within several business days.

Regards, Naoum Gitnik.