T2080RDB (ACCESS TO C293 Coprocessor)

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T2080RDB (ACCESS TO C293 Coprocessor)

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manoloruiz
Contributor III

Hi,

I am creating a PCI driver to access to the C293 Coprocessador which is in the board T2080RDB. Everything is ok when I load my driver. I can access to two memories:

c20000000-c2fffffff : /pcie@ffe250000

  c20000000-c2fffffff : PCI Bus 0001:01

    c20000000-c200fffff : 0001:01:00.0 --> first memory (1MB)

      c20000000-c200fffff : mem0

    c20100000-c201fffff : 0001:01:00.0 --> Second memory (1MB)

      c20100000-c201fffff : mem1

I want to know what is inside of these memories. I have checked the document c29xRM but I cannot find 2 memories of 1 MBytes. Any idea where can I find theses information? what is this memories for or what I can do with them?

when I type lspci -v I can see the following:

0001:01:00.0 Power PC: Freescale Semiconductor Inc Device 0808 (rev 10) (prog-if 01)

        Flags: bus master, fast devsel, latency 0, IRQ 41

        Memory at c20000000 (32-bit, non-prefetchable) [size=1M]

        Memory at c20100000 (32-bit, prefetchable) [size=1M]

        Capabilities: [44] Power Management version 3

        Capabilities: [4c] Express Endpoint, MSI 00

        Capabilities: [88] MSI: Enable- Count=1/16 Maskable- 64bit+

        Capabilities: [100] Advanced Error Reporting

        Kernel driver in use: pci

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yipingwang
NXP TechSupport
NXP TechSupport

Hello manolo ruiz,

The first 1M inbound window(BAR0) is used to access CCSR memory mapped registers.

The second 1M inbound memory window BAR1 is used to access other memory region mapped into this window.


Have a great day,
Yiping

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2,557 次查看
yipingwang
NXP TechSupport
NXP TechSupport

Hello manolo ruiz,

The first 1M inbound window(BAR0) is used to access CCSR memory mapped registers.

The second 1M inbound memory window BAR1 is used to access other memory region mapped into this window.


Have a great day,
Yiping

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manoloruiz
Contributor III

Thanks a lot Yiping. I have another question. I am trying to write in thoses memories. For example, I tried to write 1 each 8 bit. When I read these position, there are only a few bit which change to 1. Why is it happening this?

How many bit has each address 32 or 64?

BR

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yipingwang
NXP TechSupport
NXP TechSupport

Hello manolo ruiz,

You could refer to the source code of the package skmm-host.

Please use the command "bitbake skmm-host -c patch -f" to get source code in build_<platform>_release/tmp/work/<platform>-fsl-linux/skmm-host/git-r0/git.

Please refer to the function "pcidma_rc2ep_test" in pci_dma_test/pci_dma_test.c.


Have a great day,
Yiping

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