T2080 IFC NAND FLASH READ PROBLEM

[karunakaranradh]

Dear All,

We are using our own customized T2080 processor board. NOR (CS0 and CS1) and NAND (CS3 and CS4) Flash are connected in the IFC controller. The NOR flash configured in software as ADM MODE 0, CSOR0[ADM_SHFT] = 0 and Hardware signals are routed to NOR flash:

IFC_A[16:30]    ->    A[14:0]

IFC_AD[4:15] -> latch -> A[26:15]

IFC_AD[0:15]    <->    DQ[15:0]

As per this configuration, NOR Flash are working fine. In RCW bit 410-411 are configured for IFC_A[28:31] line, I unable to configure for IFC_RB_B[2:4] because of hardware limitation.

So that, I am not using the R/B signal in NAND flash.

In NAND flash driver, I can able to read the device ID and Manufacture ID using 0x90 command. but read value zero in command 0xEC (Read Parameter command).

1) it is possible to use NAND Flash without R/B signal?

2) it is possible to configure the IFC_A[31] bit alone as IFC_RB_B[4]?

[Pavel]

1) If R/B signal is not used, the end of operation can be detected reading status register of the NAND Flash.

The other method consists of using a delay after any operation of the NAND Flash. This delay especially needed for erasing/writing operations.

For example Micron MT29F256G08 datasheet shows the following timing parameters:

Array performance

– Read page: 50μs (MAX)

– Program page: 900μs (TYP)

– Erase block: 3ms (TYP)

2) The IFC_A[31] pin can be configured as Group B IFC pins only IFC_A[28:31. See the IFC_GRP_B_BASE field.

Have a great day,
Pavel

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[karunakaranradh]

Hi Pavel,

Thanks for your reply,

Changes are made in hardware, R/B signal of both NAND flash are connected to CS0 R/B# signal of the processor by external jumper wire.

Now ECh command are read properly from the NAND flash.

Regards

Karunakaran R

[vidyasagartata]

Dear Karunakaran Radhakrishnan,

We are using 32GB nand device part number MT29F256G08CMCBBH2 in customized t2080 card.

We are using IFC_CS1, IFC_CS2, IFC_CS3 and IFC_CS4 to connect nand LUN0, LUN1, LUN2 and LUN3 respectively.

RB and WP signals are mapped in 32bit mode from processor to nand flash .

Our NAND Organization is.

– Page size x8: 8936 bytes (8192 + 744 bytes)
– Block size: 256 pages (2048K + 186K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 64Gb: 4096 blocks;
128Gb: 8192 blocks;
256Gb: 16,384 blocks

  We have configured uboot:

#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_BASE            0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)

#define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
                                | CSPR_MSEL_NAND         /* MSEL = NAND */ \
                                | CSPR_V)
/*#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) */
#define CONFIG_SYS_NAND_AMASK   IFC_AMASK(8192*1024*1024)


#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
                                | CSOR_NAND_ECC_MODE_8  /* 4-bit ECC */     \
                                | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
                                | CSOR_NAND_PGS_8K      /* Page Size = 2K */\
                                | CSOR_NAND_SPRZ_CSOR_EXT       /* Spare size = 64 */\
                                | CSOR_NAND_PB(256))    /*Pages Per Block = 64*/

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
                                        FTIM0_NAND_TWP(0x18)    | \

 FTIM0_NAND_TWCHT(0x07)  | \
                                        FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
                                        FTIM1_NAND_TWBE(0x39)   | \
                                        FTIM1_NAND_TRR(0x0e)    | \
                                        FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
                                        FTIM2_NAND_TREH(0x0a)   | \
                                        FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_DDR_LAW         11
#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE      1
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 8192)

Also changed value of #define CSOR_NAND_ECC_MODE_8            0x30000000 in  include/fsl_ifc.h as it is 40bit ECC.

Below is the u-boot log:

U-Boot 2016.01 (Jun 26 2017 - 09:25:07 +0530)

CPU0:  T2080E, Version: 1.1, (0x85380011)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:899.910 MHz, CPU1:899.910 MHz, CPU2:899.910 MHz, CPU3:899.910 MHz,
       CCB:666.600 MHz,
       DDR:799.980 MHz (1599.960 MT/s data rate) (Asynchronous), IFC:166.650 MHz
       FMAN1: 599.940 MHz
       QMAN:  333.300 MHz
       PME:   666.600 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 1406001b 08000000 00000000 10000000
       00000010: 6d2d0002 7010ac00 fc027000 61000000
       00000020: 00200000 00000000 00000000 0002b3fc
       00000030: 00000100 0080000d 00000000 00000004
I2C:   ready
Board: T2080RDB, NOR vBank1
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=125.00MHz
SD2_CLK1=125.00MHz, SD2_CLK2=125.00MHz
SPI:   ready
DRAM:  Initializing....Configuring DDR for 1599.960 MT/s data rate

2 GiB left unmapped
4 GiB (DDR3 CC, 32-bit CC_test, CL=14, ECC on CCC)
VID: Could not find voltage regulator on I2C.
Warning: Adjusting core voltage failed.
Flash: 256 MiB
L2:    2 MiB enabled
Corenet Platform Cache: 512 KiB enabled
Using SERDES1 Protocol: 109 (0x6d)
Using SERDES2 Protocol: 45 (0x2d)

SRIO1: enabled

SRIO2: enabled
SEC0: RNG instantiated
NAND:  fsl_ifc_cmdfunc: error, unsupported command 0x5.
fsl_ifc_read_buf beyond end of buffer (48 requested, 0 available)
8192 MiB
MMC:   FSL_SDHC: 0
EEPROM: Invalid ID (aa 55 aa 55)
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled


PCIe4: Endpoint, undetermined, regs @ 0xfe270000
PCIe4: Bus 00 - 00
In:    serial
Out:   serial
Err:   serial
Net:   Fman1: Uploading microcode version 106.4.17
PHY reset timed out
PHY reset timed out
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3 [PRIME], FM1@DTSEC4, FM1@TGEC1, FM1@TGEC2
Hit any key to stop autoboot:  0

Nand info also shows correct page size and oob size.

Please find data sheet of NAND flash and design in attachment.

Thanks,

Vidya

[karunakaranradh]

Hi Vidya Sagar,

Your NAND Flash have four independent die in a single chip (each chip have 8Gb memory). So, In code you have to consider as 4 device.

The following macro need to configure in your code.
CONFIG_SYS_CSPR1_EXT
CONFIG_SYS_CSPR1
CONFIG_SYS_AMASK1
CONFIG_SYS_CSOR1
CONFIG_SYS_CSOR1_EXT
CONFIG_SYS_CS1_FTIM0
CONFIG_SYS_CS1_FTIM1
CONFIG_SYS_CS1_FTIM2
CONFIG_SYS_CS1_FTIM3

CONFIG_SYS_CSPR2_EXT
CONFIG_SYS_CSPR2
CONFIG_SYS_AMASK2
CONFIG_SYS_CSOR2
CONFIG_SYS_CSOR2_EXT
CONFIG_SYS_CS2_FTIM0
CONFIG_SYS_CS2_FTIM1
CONFIG_SYS_CS2_FTIM2
CONFIG_SYS_CS2_FTIM3

CONFIG_SYS_CSPR3_EXT
CONFIG_SYS_CSPR3
CONFIG_SYS_AMASK3
CONFIG_SYS_CSOR3
CONFIG_SYS_CSOR3_EXT
CONFIG_SYS_CS3_FTIM0
CONFIG_SYS_CS3_FTIM1
CONFIG_SYS_CS3_FTIM2
CONFIG_SYS_CS3_FTIM3

CONFIG_SYS_CSPR4_EXT
CONFIG_SYS_CSPR4
CONFIG_SYS_AMASK4
CONFIG_SYS_CSOR4
CONFIG_SYS_CSOR4_EXT
CONFIG_SYS_CS4_FTIM0
CONFIG_SYS_CS4_FTIM1
CONFIG_SYS_CS4_FTIM2
CONFIG_SYS_CS4_FTIM3

Out of above 4 chip select IFC macros, one only may be configured in your configuration file. so update remaining chip select value also.

Note: update/configure TLB and LAW registers to access for new NAND base address.

#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE , <NAND BASE2 ADDRESS>,<NAND BASE3 ADDRESS>,<NAND BASE4 ADDRESS>}
#define CONFIG_SYS_MAX_NAND_DEVICE      4

Since your enabled CSOR_NAND_SPRZ_CSOR_EXT in "CONFIG_SYS_CSOR(X)" configuration, you must defined CONFIG_SYS_CSOR(X)_EXT spare size as per your datasheet (744 bytes).

Regards,
Karunakaran R