T042 PLL not locking - set to "kill" in status registers

[danfitzgerald]

Hi All - Has anyone seen Platform, DDR, Core complex clocks all showing the "kill" bit set in their respective status registers?  We have a valid single ended SYSCLK, which is used to clock in the RCW, and ASLEEP is driven low, but after the RCW init phase, the internal multipliers are not working and the 100MHz SYSCLK is being used as the platform clock.  Any clues where to begin looking?

Thanks

[Bulat]

Can you clarify what means "ASLEEP is driven low"? Is it driven externally? Note, ASLEEP is an output signal on the T1042 side, so should not be be driven.

Also about RCW, did you check in any way that RCW is actually read? What is the source of the RCW?

[danfitzgerald]

Hi – Thanks for the response, good news is we found some IFC bus pull ups that had been optimised out of our CPLD, adding those back in solved the PLL issue.

Many Thanks.

[doronshaanan]

Hi

I face the same problem with my board.

I appreciate if you can let me know which signals solve the problem

Thanks

Doron

[lifengwang]

which signals of IFC？can you tell me how to solve,I have encounter similar problems!