Possible to re-enable ECC when the DDR controller is running, on T1040?

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Possible to re-enable ECC when the DDR controller is running, on T1040?

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mathiasparnaude
Contributor III

Hello

To become more familiar with the DDR controller and its ECC part, I wanted to cause some errors and check the status after. I use a T1040RDB board.

I followed a procedure for the PowerQUICC III processors found in the application note AN3532, titled "Error Correction and Error Handling on PowerQUICC™ III Processors". The idea is to write a pattern in memory (so the ECC byte is set accordingly), to turn ECC off, to change the pattern and to enable again ECC, read the pattern and see the result of the caused mismatch between the value in memory and its associated ECC byte.

With the T1040, I get a Machine Check exception when enabling again ECC. Is it only possible to enable ECC before the initialization of the memory controller?

I will continue my investigations using error injection mechanisms.

Anyway, thank you in advance if you can provide the information about the capability to re-enable ECC after memory initialization.

Mathias

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Bulat
NXP TechSupport
NXP TechSupport

It is absolutely abnormal way to dsiable ECC, change memory content and enable ECC again. You have got expected result: Machine Check exception at memory read operations due to multiple-bit ECC errors.

Error injection mechanism is more correct way, it allows to inject a single bit ECC errors that can be corrected by the HW and do not cause MCE events.

Regards,

Bulat

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Bulat
NXP TechSupport
NXP TechSupport

It is absolutely abnormal way to dsiable ECC, change memory content and enable ECC again. You have got expected result: Machine Check exception at memory read operations due to multiple-bit ECC errors.

Error injection mechanism is more correct way, it allows to inject a single bit ECC errors that can be corrected by the HW and do not cause MCE events.

Regards,

Bulat

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mathiasparnaude
Contributor III

Thanks Bulat.

Yesterday, I investigated the error injection mechanism and succeeding in having single-bit errors detected. Causing multiple-bit errors led to Machine Check exception ... what makes your explanation even more logical now (except I was only playing with a single-bit error ... maybe a side effect).

I will keep the initial idea far away from me and will continue with error injection only!

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