Flash U-boot using SRAM

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Flash U-boot using SRAM

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vinothkumars
Senior Contributor III

Hi All,

I am using Lauterbach Trace32 Debugger with T4160RDB board, We are trying flash with DDR but DDR controller have some issue so, we are trying with SRAM flash. I want to flash and boot u-boot alone using sram.

Here, I have the question.

1. What are the configuration want to do for SRAM NOR flash in u-boot side?

2. How to build the small size u-boot image for u-boot debugging?

If anyone experience in lauterbach, please provide the script or document for sram nor flash. 

Regards,

VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP TechSupport
NXP TechSupport

SPL executed from SRAM is required for SD and NAND boot because direct code execution from these devices is not possible - it is required to read block of data to SRAM and execute it from there.

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vinothkumars
Senior Contributor III

Hi All,

I built the u-boot (u-boot-spl.bin) image with small size by setting T4240RDB_SDCARD_defconfig in machine configuration file. 

I want to use NOR flash to flash this u-boot-spl.bin. As per the document (https://www.nxp.com/docs/en/supporting-information/QORIQ-SDK-2.0-IC-REV0.pdf ) NOR flash memory map as 0xEFF40000 for u-boot. But, if I look the u-boot-spl.map the address is 0xFFFD8000 and I change into 0xEFF40000 for NOR flash.

Please verify above,

SRAM NOR flash (0xEFF40000 - 0xEFFFFFFF) and now, I start u-boot debugging

In u-boot debugging (mentioned:-eff425b8: 91 49 0c 00 stw r10,3072(r9)) I got some unwanted jumps.

eff42590 <disable_law>:
eff42590: 81 42 00 b0 lwz r10,176(r2)
eff42594: 39 20 ff fe li r9,-2
eff42598: 5d 29 18 3e rotlw r9,r9,r3
eff4259c: 54 63 20 36 rlwinm r3,r3,4,0,27
eff425a0: 7d 29 50 38 and r9,r9,r10
eff425a4: 39 40 00 00 li r10,0
eff425a8: 91 22 00 b0 stw r9,176(r2)
eff425ac: 39 23 00 08 addi r9,r3,8
eff425b0: 3d 29 fe 00 addis r9,r9,-512
eff425b4: 7c 00 04 ac sync
eff425b8: 91 49 0c 00 stw r10,3072(r9)
eff425bc: 39 03 00 04 addi r8,r3,4
eff425c0: 3d 08 fe 00 addis r8,r8,-512
eff425c4: 7c 00 04 ac sync
eff425c8: 91 48 0c 00 stw r10,3072(r8)
eff425cc: 3c 63 fe 00 addis r3,r3,-512
eff425d0: 7c 00 04 ac sync
eff425d4: 91 43 0c 00 stw r10,3072(r3)
eff425d8: 7c 00 04 ac sync
eff425dc: 81 29 0c 00 lwz r9,3072(r9)
eff425e0: 0c 09 00 00 twi 0,r9,0
eff425e4: 4c 00 01 2c isync
eff425e8: 4e 80 00 20 blr

Regards,

VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP TechSupport
NXP TechSupport

> I built the u-boot (u-boot-spl.bin) image with small size by setting

> T4240RDB_SDCARD_defconfig in machine configuration file. 

> I want to use NOR flash to flash this u-boot-spl.bin.

This approach is not correct.

The SPL is not needed for the NOR Flash U-Boot, because SDRAM can be initialized by executing code directly from NOR Flash.

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vinothkumars
Senior Contributor III

Hi, 

Thank you for your reply.

I am using SRAM instead of DDR.

Is it possible to flash spl binary through the nor?

I am not clear, why because? spl image only load by SDcard and NAND as per document.

Regards,

VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP TechSupport
NXP TechSupport

SPL executed from SRAM is required for SD and NAND boot because direct code execution from these devices is not possible - it is required to read block of data to SRAM and execute it from there.

View solution in original post

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vinothkumars
Senior Contributor III

Thank you

Regards,

VinothS

Regards,
Vinothkumar Sekar
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vinothkumars
Senior Contributor III
disable_non_ddr_law function have ddr releated thing and all law entries. But, we don't want the ddr now and we needs to disable all law's expect the configured law in script.
Regards,
VinothS
Regards,
Vinothkumar Sekar
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