## Display Interface Unit's Refresh Rate

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## Display Interface Unit's Refresh Rate

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Contributor II

Dear all,
I want to use Display Interface Unit of T1042. But I want to output my video as 1024x768 RGB output at a refresh rate of 50 Hz.

I am using sysclk of 100 MHz.

I would be grateful if someone suggests me about the PLL setting for Platform clock and then recommended settings for Pixel Clock.

(Platform clock must be in between 300-600 MHz and Pixel Clock Must be less than or equal to Platform Clock / 4 )

rr =                                           pix clk
(delta_x + fp_h + pw_h + bp_h) x (delta_y + fp_v + pw_v + bp_v)

What will be the values of other parameters to get a refresh rate of 50 Hz ?

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• ### QorIQ T1 Devices

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1 Solution
144 Views
NXP TechSupport

Have a great day,

I am not sure what do you mean. You already have written correct expression for frame rate. So substitute into it  rr = 50 Hz, delta_x=1024, delta_y=768.  The sync pulse, front porch and back porch widths are defined by used LCD (or any display you can use with the DIU). You should look for these parameters in the display data sheet. Using minimal 1 pixel clock width for these widths we can estimate that pixel clock should be greater than 39.5 MHz.  Because sysclk is 100 MHz then you can get platform frequency 100*n MHz where n=3,4,5,6 - see RCW[SYS_PLL_RAT]. So there may be not exact solution because pixel clock frequency is platform clock frequency divided by integer value.

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2 Replies
145 Views
NXP TechSupport

Have a great day,

I am not sure what do you mean. You already have written correct expression for frame rate. So substitute into it  rr = 50 Hz, delta_x=1024, delta_y=768.  The sync pulse, front porch and back porch widths are defined by used LCD (or any display you can use with the DIU). You should look for these parameters in the display data sheet. Using minimal 1 pixel clock width for these widths we can estimate that pixel clock should be greater than 39.5 MHz.  Because sysclk is 100 MHz then you can get platform frequency 100*n MHz where n=3,4,5,6 - see RCW[SYS_PLL_RAT]. So there may be not exact solution because pixel clock frequency is platform clock frequency divided by integer value.

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