T1042 Addressing Algorithm

cancel
Showing results for 
Search instead for 
Did you mean: 

T1042 Addressing Algorithm

621 Views
faizmajeed
Contributor III

HI!

This discussion is related to T1042 to get understanding about its addressing algorithm. For Example core e5500 generate some address to request a data. This address is compared in LAW (Local Access Window) which give responsibility to some memory controllers to handle this transaction on the basis of target id. Now we have to discuss that

what type of address these Memory controllers recieve

how they decode this address and decide which chip select should be enabled

what base address should be selected in for different chip select registers For Example (in case of IFC values of  IFC_CSPRn_EXT and IFC_CSPRn ).

We have to focus on IFC controller.

Thank You

Labels (1)
0 Kudos
13 Replies

296 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

Local Access Window configures which memory controller this particular memory access will be targeted. When the access reaches IFC controller, IFC controller decides which particular CS line to assert by use base address and address mask information, stored in CSPRn_EXT[BA_EXT], CSPRn[BA] and IFC_AMASKn[AM] fields, where "n" is CS line number. For each CS line IFC controller has its own set of base address and mask, so there is no problem to determine which particular pair of base address and mask this particular access corresponds to.


Have a great day,
Alexander
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos

296 Views
faizmajeed
Contributor III

core's MMU generates a transaction with 36-bit target address. it is compared with LAW

MMU_address [0:23] == LAW_LAWBARHn[28:31] + LAWBARLn[0:19] 

if it is true for IFC controller then

MMU_address[35:28] ,(AMn[0:15]&MMU_address[27:12]) == BASE_ADDRn[0:7], (BASE_ADDRn[8:23] & AMn[0:15]) is used to enable the chip select.

This mean that we should set the base address of IFC_CSPRn and IFC_CSPRn_EXT so that it should be equal to base address of LAW that is specific for IFC ?

if it is true then what would be address that will go on IFC output address pins?

0 Kudos

296 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

If you have only one CS enabled and configured in your IFC, than yes, base address and mask should be set the same, as you have it configured in Local Access Window for IFC. In case if your IFC has more than one CS line enabled and configured, than you can have all IFC spaces covered by one Local Access Window.

0 Kudos

296 Views
faizmajeed
Contributor III

 In my case, IFC has more than one CS line enabled and configured,then how one local access window can covered all the CS. the algorithm covered in the manual is only for one CS. can you please tell me using some kind of example.

0 Kudos

296 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

Please specify your desired IFC memory map - how each CS will be configured (base address and mask)

0 Kudos

296 Views
faizmajeed
Contributor III

Actually i am using 3 NOR flashes. 1 for Booting and 2 as an Application flash. I have also interfaced 1 NVRAM(asynchronous)  as NOR. 

NOR MT28EW01GABA1LPC-1SIT  (1Gb)

NVRAM CY14V104NA-BA45XI  (4096kb)

Now i have just completed their pin connections using reference manual and reference schematics. Now i can not understand about the base address and extended base addresses that what should i set these addresses. Please give some suggestion how can i set the value of these registers for all of my flashes and NVRAM.

0 Kudos

296 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

Each CS line in IFC controller is configurable and has its own base address and address mask. So, each NOR flash base address and mask is configurable. There is no "default" or "recommended" address map, particular address map is up to designer. Typical address map (copied from T1040 QDS board Reference Manual):

pastedImage_2.png


Have a great day,
Alexander
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos

296 Views
faizmajeed
Contributor III

Thanks Alexander. can you please provide me the document "T1040 QDS board Reference Manual".

I cannot access it. 

0 Kudos

296 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

Sorry, we do not offer this board anymore, so the documentation for this board is not available publicly.

Sorry for reference to this document, but actually it was used only as example of memory map.

0 Kudos

296 Views
faizmajeed
Contributor III

how can i configure my memory map for my Flashes. suggest me some alternative, if you cannot provide me this document. 

0 Kudos

296 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

I do not understand the question, sorry. Please explain, why above example memory table is not enough to do that - what exactly unclear from this table?

0 Kudos

296 Views
faizmajeed
Contributor III

This is only for CS0. i want base addresses for CS1,CS2,CS3 also as i have four flashes.

0 Kudos

296 Views
alexander_yakov
NXP TechSupport
NXP TechSupport

The table shows IFC_CS number in 4th column. I see CS numbers 0,1,2,3,6 and 7

0 Kudos