e6500 core is a pipelined, multiple execution units architecture with
sophisticated instruction dispatch mechanism, so it may be not quite
obvious where it spends extra cycles and why. Beside that, if your
loop is polling a memory location, the timing will depend on the
cache policy, bus timing (if cache-inhibited), coherency protocol.
The suggestion in this regard is to us CodeWarrior Trace and Analysis
tools to see what exactly happens. More details can be found at the
link below:
https://freescale.sdlproducts.com/LiveContent/content/en-US/CodeWarrior_PA_Knowledge_Center/GUID-B68...
Have a great day,
Platon
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