Mithun,
Looks fine, just a few comments:
1. As VDD is higher than 2.75V, the VDD and VREG pins should not be connected together. Use a separate 0.1μF decoupling ceramic capacitor on VREG to VSS as shown in figure 2 of the datasheet.
2. In the final schematic, do not forget to connect the ADDR pin accordingly.
3. If the customer is going to use the IRQ output, use a level translator also on this line. I do not have much experience with discrete MOSFETs, I usually use an integrated solution such as the PCA9306DCUR from TI.
Regards,
Tomas