1. As you can see in the FRDM-FXS-MULTI(-B)/FRDM-KL25Z schematics and the image below, I2C signals are routed to the I2C1 module (PTC1 and PTC2 pins) of the KL25Z MCU and the INT1 output is connected to the PTA5 pin (make sure that pin #3 of J4 and pin #2 of J6 connector on the sensor expansion board are connected together). The INT1 output of the MMA8652FC is configured as a push-pull active-low output, so the corresponding PTA5 pin configuration is GPIO with an interrupt on falling edge.
The MCU is, therefore, configured as follows.
//I2C1 module initialization
SIM_SCGC4 |= SIM_SCGC4_I2C1_MASK; // Turn on clock to I2C1 module
SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK; // Turn on clock to Port C module
PORTC_PCR1 |= PORT_PCR_MUX(0x2); // PTC1 pin is I2C1 SCL line
PORTC_PCR2 |= PORT_PCR_MUX(0x2); // PTC2 pin is I2C1 SDA line
I2C1_F |= I2C_F_ICR(0x14); // SDA hold time = 2.125us, SCL start hold time = 4.25us, SCL stop hold time = 5.125us
//Configure the PTA5 pin (connected to the INT1 of the MMA8652FC) for falling edge interrupts
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; // Turn on clock to Port A module
PORTA_PCR5 |= (0|PORT_PCR_ISF_MASK| // Clear the interrupt flag
PORT_PCR_MUX(0x1)| // PTA5 is configured as GPIO
PORT_PCR_IRQC(0xA)); // PTA5 is configured for falling edge interrupts
//Enable PORTA interrupt on NVIC
NVIC_ICPR |= 1 << ((INT_PORTA- 16)%32);
NVIC_ISER |= 1 << ((INT_PORTA- 16)%32);
2. The 7-bit I2C address of the MMA8652FC is fixed value 0x1D. As shown above, the SCL line is connected to the PTC1 pin and SDA line to the PTC2 pin. The I2C clock frequency is 125 kHz.
The screenshot below shows the write operation which writes the value 0x39 to the CTRL_REG1 (0x2A).
And here is the single byte read from the WHO_AM_I register 0x0D. As you can see, it returns the correct value 0x4A.
Multiple bytes of data can be read from sequential registers after each MMA8652FC acknowledgment (AK) is received until a no acknowledge (NAK) occurs from the KL25Z followed by a stop condition (SP) signaling an end of transmission. A burst read of 6 bytes from registers 0x01 to 0x06 is shown below. It also shows how the INT1 pin is automatically deasserted by reading the acceleration output data.
3. At the beginning of the initialization, all registers are reset to their default values by setting the RST bit of the CTRL_REG2 register. The dynamic range is set to ±2g and to achieve the highest resolution, the lowest ODR (1.56Hz) and the High Resolution mode are selected (more details in AN4075). The DRDY interrupt is enabled and routed to the INT1 interrupt pin that is configured to be a push-pull, active-low output.
I2C_WriteRegister(MMA8652FC_I2C_ADDRESS, CTRL_REG2, 0x40); // Reset all registers to POR values
Pause(0x631); // ~1ms delay
I2C_WriteRegister(MMA8652FC_I2C_ADDRESS, XYZ_DATA_CFG_REG, 0x00); // +/-2g range with ~0.977mg/LSB
I2C_WriteRegister(MMA8652FC_I2C_ADDRESS, CTRL_REG2, 0x02); // High Resolution mode
I2C_WriteRegister(MMA8652FC_I2C_ADDRESS, CTRL_REG3, 0x00); // Push-pull, active low interrupt