SBC 6513CAE

[qiaoqin_wang]

i have a confusion about the 6513CAE,while the FS0B and FS1B asserted low when during start up that is the same with when SBC detect MCU error acation?

[naveenm]

Hi,

The last question on debug mode configuration is related to function of the chip so we are moving it to Power Management community for further response.

The link is here:

Re: SBC 6513CAE - NXP Community

Regards,

NaveenM

[r40959]

Yes, FS0B and FS1B are asserted low during the power up phase and when an error is detected. These 2 pins can be released only when no fault is reported/pending and when the fault error counter is cleared after several good WD refresh after RSTB is released from power up. If the application requires FSxB to be released during power up, like in Body Controller Module, FS65 is not compatible with this requirement. hoping it helps you

[qiaoqin_wang]

thanks for your reply, i also want to know why the FS0B and FS1B are asserted low during the power up phase ?

[qiaoqin_wang]

Dear all

who can help me to understand this confusion as the below show, thanks for your support.

[r40959]

Hello, we would like to refer to the datasheet (section 12.5.6.1) and safety manual (section 11.15.2). FS1B pin is the secondary safe output pin. FS1B is asserted low with a configurable delay (tDELAY) or duration (tDUR) when FS0B is asserted low (see Section 12.5.6 in datasheet). After each power-on reset or after each wake-up event (LPOFF), the FS1B pin is asserted low. Then the MCU can decide to release the FS1B pin, when the application is ready to start, which means when no fault is reported/pending and when the fault error counter is cleared after several good WD refresh (Fault error counter is at "1" at start-up or after wake-up from LPOFF if no other faults are reported) after RSTB is released from power up. We hope it helps. Best regards.