S32V234 Safety questions

[Daniel_Wax]

I have a customer I am helping with changes to FMEDA assumptions and we have these questions.

Currently we will be only modifying CORE and RAM FMEDA

FMEDA	Column	Question	Response
Core	AR3 - TVF’s	Are TVF’s enabled by Default
	T3- STM/PIT	How to enable STM/PIT using QNX has it been done before any sample code?
	K3 - ITM	How to enable ITM - sample code? Impact of disabling it?
	AS3 - Parity Protection Interconnect	Is this referring to the MEW which is capable of embedding ECC/EDC in the data
RAM	AB3 - CRC static data for MMDC0	Are we referring to Static configuration registers? Does this have to use the CRC hardware onboard the S32V? What is the impact if we use a software implementation? What if - Alternatively, we can check the register contents completely
	AG3 - CRC static data for MMDC1	Are we referring to Static configuration registers?
	AE3-ECC for MMDC1 (- not possible on cut1-	ECC on MMDC1 not possible? Could you explain?

[nxf64307]

Hello Daniel,

I hope the above query was answered over email and is clarified. Please do let me know if you have any query further associated to this. 

Also, attached the Table below with the response.

FMEDA	Column	Question	Response
Core	AR3 - TVF’s	Are TVF’s enabled by Default	yes, they are enabled always. (The FMEDA allows to disable this feature but in HW it is always enabled).
	T3- STM/PIT	How to enable STM/PIT using QNX has it been done before any sample code?	The question is unclear. The FMEDA asks whether the “System Timer (STM) is safety relevant”.  That may or may not be the case in a particular application. If yes, the errors are calculated, otherwise they are considered safe.
	K3 - ITM	How to enable ITM - sample code? Impact of disabling it?	The INTM is only available for 4 interrupts which are critical for the application. The impact can only be judged on system level. The S32V234 as such works fine without INTM. The only impact is that potential interrupt handling errors might not be detected.
	AS3 - Parity Protection Interconnect	Is this referring to the MEW which is capable of embedding ECC/EDC in the data	This is not related to MEW. This is related to the EDC used on: Main Interconnect NIC-301 Cache-coherent interconnect  CCI-400 Crossbar Switch (AXBS) Note: This is not related to protection of interconnect which is inside HPSMI. This is analyzed in the respective RAM FMEDA.
RAM	AB3 - CRC static data for MMDC0	Are we referring to Static configuration registers? Does this have to use the CRC hardware onboard the S32V? What is the impact if we use a software implementation? What if - Alternatively, we can check the register contents completely	The CRC is over the content stored in DRAM. The Fast_DMA has been designed for this purpose and is probably the fastest check and simplest implementation. However, any other check (e.g. by SW) of the content in DRAM can be used alternatively (CRC or direct comparison, etc ...). Please keep in mind that the SW executing the test may be impacted by the fault it is trying to detect (if running from code in that DRAM). If ECC is used, this CRC may not be required. If no ECC is used, it depends on the usage of the DRAM content whether such test is required or not. The check of static configuration registers is configured in column AN.
	AG3 - CRC static data for MMDC1	Are we referring to Static configuration registers?	Same as above.
	AE3-ECC for MMDC1 (- not possible on cut1-	ECC on MMDC1 not possible? Could you explain?	Cut1 has only one DRAM controller equipped with ECC: This has been changed from cut2 onwards. The comment “(- not possible on cut1” can be ignored and AE5 can be enabled (if ECC is used).

Regards,

Rupesh