Hello @piyush1 ,
The ADC module in S32K311 receives its input clock from CORE_CLK, which can be up to 120 MHz depending on your system configuration. However, the ADC uses an internal conversion clock, which is derived by dividing the input clock using the ADC.MCR[ADCLKSEL] setting:
- ADCLKSEL = 00 → divide by 1
- ADCLKSEL = 01 → divide by 2
- ADCLKSEL = 10 → divide by 4
All internal ADC timing - including sampling and conversion - is based on this divided clock. The conversion time itself is not configurable directly; it depends on resolution and averaging settings. You may refer to an explanation in this article S32K312 ADC Clock Selection
Best regards,
Pavel