s32k144 Question about Cache operation after VLPS->RUN mode transition

[Hirofumi]

I use cache enable using below cmd after reset.

LMEM->PCCRMR = 0x80000000U;/*Only R0 region is cacheable*/
LMEM->PCCCR = 0x85000001U;

Other LMEM register is used reset value.

[Questions]

When cache is enable and MCU transitions to VLPS->RUN,

Do I need to any register operation for chache ?

[lukaszadrapa]

Hi @Hirofumi 

this configuration is kept during the VLPS, no configuration is needed.

Regards,

Lukas

[Hirofumi]

Hi lukas,

Thank you for supporting.

Will the data that was read into chche memory be keep in VLPS mode?
If no, Should I need to execute invalidate cmd after transit VLPS -> RUN?

[lukaszadrapa · Accepted solution]

The content of memories (including the cache memory) is retained. Let me share some screenshots from the reference manual:

Regards

Lukas