internal clock deviation

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

internal clock deviation

跳至解决方案
1,016 次查看
yangaichimantou
Contributor I

Hi,

We need S32K to calculate high precision time.

We want to know, if we use external crystal of 16M and frequency tolerance of 1 ppm.

S32K internal clock double 10x frequency by PLL.

Then the internal time deviation may be 10 times of the external crystal deviation?

Or do we have other experiment data or calculate method?

0 项奖励
回复
1 解答
1,002 次查看
Senlent
NXP TechSupport
NXP TechSupport

Hi@yangaichimantou

yes ,you can calculate it like this, but it's not entirely accurate.

because the PLL has a filtering effect on the input source jitter, there is inherent PLL jitter on the generated output,so a completely accurate calculation is not easy to quantify.

BR!

 

 

在原帖中查看解决方案

0 项奖励
回复
1 回复
1,003 次查看
Senlent
NXP TechSupport
NXP TechSupport

Hi@yangaichimantou

yes ,you can calculate it like this, but it's not entirely accurate.

because the PLL has a filtering effect on the input source jitter, there is inherent PLL jitter on the generated output,so a completely accurate calculation is not easy to quantify.

BR!

 

 

0 项奖励
回复