Watchdog reset after entering VLPS mode

[海斌蔡]

Hi,

My program enters vlps low-power mode, and the software stays in the following position

The watchdog resets after 3 hours and 40 minutes of the software. The following is the configuration of the watchdog register when the software enters the LVPS mode.

I have two questions
1. When the software enters VLPS mode, WDOG->CNT will still increment, but the increment is very slow. Why is it not a 2 second watchdog reset but more than 3 hours?

2. Before entering VLPS mode, should the watchdog be disabled?

Thanks & Regards,

[海斌蔡]

My program enters vlps low-power mode, and the software stays in the following position

[nxf47333]

Hi Robin,

I have questions, according to RM

if i enter stop1/stop2 with Watchdog enabled(and configuration timer out is 1s), will watchdog trigger system reset after timeout.

if i enter vlps, does it mean, watchdog will production wake up event once timerout

[Robin_Shen]

Hi 海斌蔡,

According to the description of "Table 39-4. Module operation in available power modes", you don't need to disable the watchdog.
In VLPS mode, Watchdog is Async operation (STOP bit needs to be set). Async Wakeup.
I did not see you set STOP bit of SC register.
Would you please set STOP bit and then test again?

Async operation Fully functional with alternate clock source (if the selected clock source remains enabled).
"Table 39-4. Module operation in available power modes" shows that the OSC that you selected is OFF in VLPS. Please select other clock source.

Best Regards,
Robin
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