thanks Leo. demo and sch as attached.
The development board I use is S32K396-LQFP-DC, and the filtering circuits of SDADC0 AN0 and AN1 channels are shown in the following figure.

I am testing the AN2 and AN3 channels of SDADC0, and the input circuit is shown below:

I use the FIFO interrupt of SDADC to transfer the collected data into the data array, and the FIR filter is not enabled in SDADC. I measured a 2V, 10kHz sinusoidal signal and the resulting data array is plotted in the following image.

In this case, SDADC works fine; However, after the FIR filter is enabled, there are problems with the output data. The filtered converted data appears incomplete, with an abnormal downward shift in the signal, as shown in the figure below.
