S32K358 - Linker script modification for M7_2

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

S32K358 - Linker script modification for M7_2

452 Views
sathishkumar_sunmugavel
Contributor III

Hi Everyone,

I’m currently working on the S32K358 board and aiming to run my application on Core 2. I have successfully compiled the code for Core 2, but I ran into a limitation with the .bss section size.

I initially modified the linker script to increase the size of the .bss section, and with the below changes it worked correctly.

sathishkumar_sunmugavel_0-1751276214247.png

However, I noticed that certain memory regions remain unused. To optimize memory usage, I tried further modifying the linker script to utilize these available regions.

After below changes, the application builds successfully, but I encounter a hard fault at runtime.

sathishkumar_sunmugavel_1-1751276350341.png

Could anyone help me understand why this hard fault is occurring? Also, what is the correct and safe way to modify the linker script to effectively use the available memory for Core 2 without running into such faults?

Thanks in advance!

Best Regards,
Sathish.




0 Kudos
Reply
4 Replies

433 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Hi, I would recommend leaving all sections as they are, just moving their starting addresses and sizes as needed.

0 Kudos
Reply

429 Views
sathishkumar_sunmugavel
Contributor III

Hi @davidtosenovjan 

From my analysis:

  • The *_c2 sections are not used in the M7_0 linker script.

  • The *_c0 sections are not used in the M7_2 linker script.

  • The *_c1 sections are not used in either M7_0 or M7_2 linker scripts.

I had removed these sections myself to keep only the memory regions relevant to each core in their respective linker scripts.

I’ve also verified the generated ELF file, and the section-to-memory mappings are correct.

Could you please clarify why you recommend leaving all sections as they are?

Additionally, the memory regions int_sram_c1, int_sram_fls_rsv_c1, int_sram_no_cacheable_c1 are currently unused in the linker script. I would like to utilize this memory for Core 2.

Could you please guide me on how this memory can be properly utilized by adjusting their starting addresses and sizes?

Thanks,
Sathish.

0 Kudos
Reply

407 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

Could you attach whole your linker command file?

0 Kudos
Reply

449 Views
sathishkumar_sunmugavel
Contributor III

I have uploaded the wrong screenshot for non-working case. Please find the right one here.

sathishkumar_sunmugavel_0-1751277097459.png



Regards,
Sathish.

0 Kudos
Reply