S32K344 EVB FS26 debug pin voltage is 7.2, How can it enter debug mode(VDBG(2.5V < debug pin < 6V))?

[Eason_L]

Hi,

Accroding to S32K344 EVB circuit.

1. The votage of FS26_VDEBUG is 7.2 (12*15/25), How can it enter debug mode(VDBG(2.5V < debug pin < 6V))?

2. What's the purpose of BJT circuit? It makes debug pin voltage drop to 0V after ~80ms

Thanks,

Eason

[Senlent · Accepted solution]

Hi@Eason_L

1.you may forget still have 10K resistor in the picture

2.After VBAT_SW is powered on, it will turn on Q1 and pull FS26_VDEBUG low to 0V

[1260784871]

after resistance R478 , the voltage test is still 7.2v，why？

[Eason_L]

Hi Senlent,

Thanks for the first question. About second question, Why does it need to turn on Q1 and pull FS26_VDEBUG low to 0V? It seems unnecessary.

[Senlent]

Hi@Eason_L

For OTP mode(Flash MODE), it is necessary.

please take a look at the below two chapters:

Rev.3

Chapter 23 OTP and Debug mode

When the OTP configuration is complete, the fail-safe state machine will start in Debug mode when the voltage at the DEBUG pin is below VNORM_max (NXP recommends applying 0 V or GND).

and Figure 72. OTP mode flowchart until safety outputs release