Hi NXP experts,
As the RM mentiones, the PLLDIG supports a down-spread modulation.
Could you help provide more details about the function, such as the steps about how to enable/disable it?
Thansk in advance,
Gavin
已解决! 转到解答。
This feature is available directly in the S32DS clock configurator as you can see in the screenshot below:
davidtosenovjan_0-1706722725592.png
在原帖中查看解决方案