S32K1XX LPSPI Host req

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S32K1XX LPSPI Host req

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yuegao1996
Contributor II

 in the ref manual it says that host request source could be configured as HREQ pin or trigger source though register CFGR0[HRSEL].  But i am not clear about the trigger itself. what kind of trigger it is. is it a pin signal ?

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StanoA
NXP TechSupport
NXP TechSupport

Hello Yuegao,

The trigger option is described in the Chapter 19 – Trigger MUX Control. For the LPSPI0 it is out92 - TRGMUX_LPSPI0 – on Figure 19-3, page 422 of S32K1XX_RM:

https://www.nxp.com/webapp/Download?colCode=S32K1XXRM

So the trigger is the output signal from Trigger MUX.

I hope it will help you in your study.

Best Regards,

Stano.

 

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StanoA
NXP TechSupport
NXP TechSupport

Hello Yuegao,

The trigger option is described in the Chapter 19 – Trigger MUX Control. For the LPSPI0 it is out92 - TRGMUX_LPSPI0 – on Figure 19-3, page 422 of S32K1XX_RM:

https://www.nxp.com/webapp/Download?colCode=S32K1XXRM

So the trigger is the output signal from Trigger MUX.

I hope it will help you in your study.

Best Regards,

Stano.

 

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