Our project uses S32K148 ADC0 and ADC1, and each ADC is configured with 8 channels. The test found that the last three channels could not obtain data.
Hi guochuan,
I think the problem can come from this parameter is so small to convert data on all channels. So, you can try to adjust it.
This is its description
For example:
ADC's clock frequency is 40 MHz and prescaler value for frequency is 1.
PDB's clock frequency is 80MHz get from SYS_CLK
Follow to above expression for 1 ADC's channel: "ADC TOTAL CONVERSION TIME = Sample Phase Time (set by SMPLTS+1) + Hold Phase (1 ADC Cycle) + Compare Phase Time (8-bit Mode=20 ADC Cycles, 10-bit Mode=24 ADC Cycles,
12-bit Mode=28 ADC Cycles) + Single or First continuous time adder (5 ADC cycles + 5 bus clock cycles)."
SMPLTS:
I used 12 bit Mode.
In my case, ADC cycle = Bus cycle.
ADC TOTAL CONVERSION TIME = (255 + 1) + 1 + 28 + 10 = 295.
I have this parameter:
So, I have: ADC TOTAL CONVERSION TIME = 295 * 8 * 8 (channels) = 18880 (cycles)
This parameter Adc Delay Next PDB (0 -> 65535) have to ensure enough time to convert all pre-triggers in channel 0 and this value will be written as counter of PDB. So, we need to convert to PDB's cycles before write it into the register.
(18880/ 40 * 80 = 37760)
Adc Delay Next PDB (0 -> 65535) have to configure bigger than 37760.
Best regards,
Nhi
