S32K144 UART FIFO Example

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S32K144 UART FIFO Example

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harish_g2
Contributor II

Hi All,

Is anyone used UART FIFO for S32K144?

LPUART2->CTRL &= (0xC0000); // Disable TE and RE for Setting FIFO
LPUART2->FIFO |= 0x000000ff; // Enable TX and RX FIFO for 256 bytes 
LPUART2->CTRL |= (0xC0000); // Enable TE and RE after for Setting FIFO

After this also am receiving only 4 bytes and RX OverFlow is set. 

Please let me know if anyone has done these experiments. 

Thanks in Advance..!

Harish G

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harish_g2
Contributor II

Hi Diana,

Thanks for the response. Please release errata sheet, your user manual gives a different impression. However, if it's not possible to use FIFO, I'm okay to use DMA. But I have another question LPUART MATCH can trigger interrupt asper the user manual. we found it's not working either. please confirm.

The procedure followed for this is given in s32K reference manual section 51.4.4.2.6 Match On Match Off operation
1. Configured UART MATCH Register 
2. Enabled MATCH Interrupts 
    LPUART0->BAUD &= ~(0xC0080000); // Clearing MAE1 and MAE2 bits for writing MATCH registers
    LPUART0->MATCH = 0x00320031; // Match1: '1' and Match2: '2'
    LPUART0->BAUD |= 0xC0080000; // Setting MAE1, MAE2 Bits and BAUDCFG 10 - Match ON OFF operation
    LPUART0->CTRL |= LPUART_INT_MATCH_ADDR_ONE; // Enable MATCH 1 Interrupt
    LPUART0->CTRL |= LPUART_INT_MATCH_ADDR_TWO; // Enable MATCH 2 interrupt
Our observation - We are getting Interrupt for MATCH1 only and no interrupt triggered for MATCH2 
Please clarify..!
Regards,
Harish
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dianabatrlova
NXP TechSupport
NXP TechSupport

Hi Harish,

I understand that it can be confusing, however, the RM is correct:

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Regarding your second question:

The CTRL[MA2IE] actually enable MA2F interrupt. If MA2F is not set the interrupt is not generated.

The section 51.4.4.2.6 Match On Match Off operation describes that " The character that matches
MATCH[MA2] and all following characters are discarded". That is mean the character that matches
MATCH[MA2] is not placed to receive data buffer. If the character is not moved into receive data buffer the MA2F is not set and the interrupt does not occur.

You can try a simple test where BAUD[MAEN2] = 0. After that, the character which matches MA2 is moved to the receive data buffer and the MA2F is set, but the following data will be also moved into the receive data buffer (the data won't be discarded as is described in the "Match On and Match Off" section). 

I hope it helps.

Best Regards,

Diana

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harish_g2
Contributor II

Hi Diana,

Thank you for the detailed info. We will do some experiment on this and get back to you.

I have few doubts on HW Flow Control for UART in S32K144.

We are configuring MODIR register to 0x9 // TXCTSE bit 1 and RXRTSE=1 and later we are not receiving any data from the modem, we don't know that transmitted data received by modem or not also.

And we wanted to know that what are bits to be configured for Full Modem support in MODIR register (RTS and CTS lines are interconnected b/w microcontroller and modem). 

Please let us know what are bits to be configured in MODIR register so that RX Overrun Interrupt should not occur even if don't read DATA register for some time.

Regards,

Harish G

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dianabatrlova
NXP TechSupport
NXP TechSupport

Hi Harish,

I'm very sorry for the delay. 

If you have an RX overrun let's check first your LPUART settings. What is your baudrate, clock settings?

Regarding hardware flow control, could you please share the screen from oscilloscope/analyzer where can be seen the RTS, CTS, Rx, Tx?

Thank you in advance.

Best Regards,

Diana

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dianabatrlova
NXP TechSupport
NXP TechSupport

Hi Harish,

Unfortunately, the TXFIFOSIZE and RXFIFOSIZE fields are read-only, the Buffer depth is only 4 datawords for the S32Kxx devices.

Best Regards,

Diana

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