Hi@AnilKumar409
modified base on the demo of S32K144_Project_FlexCan
MB1 used for receiving messages which id range of 0x100~0x107，
（in this case,0x108 need to be allocated a MB for it separately）
void FLEXCAN0_init(void)
{
#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */
uint32_t i=0;
PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */
CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
CAN0->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKsrc=0: Clock Source = SOSCDIV2 */
CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT) */
while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {}
/*!
* Good practice:
* ===================================================
* wait for FRZACK=1 on freeze mode entry/exit
*/
//Enable the individual filtering per MB and reception queue features
CAN0->MCR |= CAN_MCR_IRMQ(1);
//Disable Rx FIFO
CAN0->CTRL2 = 0 | CAN_CTRL2_EACEN(0);
CAN0->CTRL1 = 0
#if defined(S32K11x_SERIES)
|CAN_CTRL1_PRESDIV(4) /* PRESDIV=4: Sclock=PEclock/(PRESDIV+1) = 40MHz/5 = 8MHz */
#endif
|CAN_CTRL1_PSEG2(3) /* Configure for 500 KHz bit time */
|CAN_CTRL1_PSEG1(3) /* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */
|CAN_CTRL1_PROPSEG(6) /* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */
|CAN_CTRL1_RJW(3) /* so PRESDIV = 0 */
|CAN_CTRL1_SMP(1); /* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */
/* PSEG1 = PSEG2 = 3 */
/* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */
/* RJW: since Phase_Seg2 >=4, RJW+1=4 so RJW=3. */
/* SMP = 1: use 3 bits per CAN sample */
/* CLKsrc=0 (unchanged): Fcanclk= Fosc= 8 MHz */
for(i=0; i<128; i++ )
{ /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words */
CAN0->RAMn[i] = 0; /* Clear msg buf word */
}
for(i=0; i<16; i++ )
{ /* In FRZ mode, init CAN0 16 msg buf filters */
CAN0->RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */
}
//CAN0->RXMGMASK = 0x1FFFFFFF; /* Global acceptance mask: check all ID bits */
CAN0->RAMn[ 4*MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */
/* EDL,BRS,ESI=0: CANFD not used */
/* CODE=4: MB set to RX inactive */
/* IDE=0: Standard ID */
/* SRR, RTR, TIME STAMP = 0: not applicable */
/* Node B to receive msg with std ID 0x555 */
CAN0->RAMn[ 4*MSG_BUF_SIZE + 1] = 0x555 << 18; /* Msg Buf 4, word 1: Standard ID = 0x555 */
CAN0->RAMn[ 1*MSG_BUF_SIZE + 0] = 0x04000000;
CAN0->RAMn[ 1*MSG_BUF_SIZE + 1] = 0x100 << 18;//Standard ID = 0x100
//receive range of standard IDs of 0x100~0x107
CAN0->RXIMR[1] = 0x1FE3FFFF;
CAN0->MCR |=((0x0000001F) | (1 << 17));//SRXDIS = 1,MAXMB = 32
CAN0->MCR &=~CAN_MCR_HALT_MASK; //Netate HALT bit
while ((CAN0->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {}
/* Good practice: wait for FRZACK to clear (not in freeze mode) */
while ((CAN0->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {}
/* Good practice: wait for NOTRDY to clear (module ready) */
}
main.c
When a frame with ID 0x100 to 0x107 is received, the led light will flash
for (;;)
{ /* Loop: if a msg is received, transmit a msg */
if ((CAN0->IFLAG1 >> 4) & 1) { /* If CAN 0 MB 4 flag is set (received msg), read MB4 */
FLEXCAN0_receive_msg (); /* Read message */
rx_msg_count++; /* Increment receive msg counter */
if (rx_msg_count == 1000) { /* If 1000 messages have been received, */
PTD->PTOR |= 1<<16; /* toggle output port D16 (Green LED) */
rx_msg_count = 0; /* and reset message counter */
}
FLEXCAN0_transmit_msg (); /* Transmit message using MB0 */
};
if((CAN0->IFLAG1 >> 1) & 1)
{
CAN0->IFLAG1 = 0x00000002; /* Clear CAN 0 MB 1 flag without clearing others*/
PTD->PTOR |= 1<<16;
}
}
BR!
