Hi PeterS,
Thanks for the response.
I am using s32k144 with 20 MHz crystal.
I wanted to know can bit time setting for 500KHz , and ctrl setting as per below snap for the same sample code,sys clk selected is 80Mhz

so what should i set for below register in the sample code such that the can communication can take place for 8Mhz Sclock (derived from above CTRL1 register setting) and 500KHz bitrate for Can communication.

In canpal flexcan sample code , i have done below changes , .enablefd=false, .length = 8, payload selected as 8byte and disabled the FEATURE_CAN_HAS_FD macro in the code.
Please let me know if any other register value needs to be updated for standard CAN changes and also confirm the CAN bite setting for register phaseSeg1, phaseSeg2,predivider,propSeg and rJumpwidth.
Thanks.