S32K Interrupt Monitor (INTM) Functionality Clarification

[BalasubramaniyanS]

We are implementing interrupt monitoring on the S32K platform and seek clarification on the INTM peripheral's measurement methodology and Timer register interpretation.

Specific Technical Questions:

Measurement Methodology:

Does the INTM measure the delta between consecutive interrupt occurrences, or

Does it measure the latency between interrupt assertion and the first instruction execution of the ISR?

Timer Register Interpretation:

In our current implementation monitoring ADC and STM interrupts, we observe Timer register values ranging from 0xFE to 0x120.

Are these values representing raw clock cycles or a scaled time period?

What is the reference clock source for these measurements?

This information is critical for our interrupt latency optimization efforts and system timing analysis.

Thank you for your assistance.

[Robin_Shen]

Hi

A1: INTM allows you to set a maximum timer count for the interrupt latency from interrupt request to interrupt acknowledge. So if you write INTM_IACK as the first instruction in your ISR, then it is what you said. (It measure the latency between interrupt request and the first instruction execution of the ISR)

INTM allows you to set a maximum timer count for the interrupt latency from interrupt request to interrupt acknowledge.png

A2: Counts the number of INTM clock cycles for a detected interrupt request to an acknowledged interrupt processing.  

16.5.6 Timer for Monitor a (INTM_TIMER0 - INTM_TIMER3).png

So this is related to the value of your AIPS_PLAT_CLK frequency.

Table 128. System module clocking INTM AIPS_PLAT_CLK.png

Best Regards,
Robin
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[Robin_Shen]

Hi

Due to the Christmas vacation period, our response times may be longer than usual. We appreciate your patience as our team navigates this busy season. 
Please be assured, we are committed to responding your inquiries as quickly as possible. 
Thank you for your understanding and happy holidays!

Best Regards,
Robin