RMII clock for S32K3

[rezrez]

Hi!

I'm designing an Ethernet interface (RMII) with S32K3 and Microchip phy and I wonder about the clocks and the directions. Based on S32K3 reference manual, page 3299, we have this two statements:

• MII_RMII_TXCLK (Clock): Input
  • MII: The external PHY provides this transmission clock, which operates at a frequency of 25 MHz in 100 Mbps mode and at 2.5 MHz in 10 Mbps mode. All transmission signals that MAC generates are synchronous to this clock, which is required for all PHY interfaces.
  • RMII: The RMII interface uses this 50 MHz clock. If you select RMII mode, MII_RX_CLK (25 MHz or 2.5 MHz) must be derived from the RMII reference clock.
• MII_RX_CLK (Clock): input
  • The external PHY provides this receive clock for the MII and RMII interfaces. The clock operates at a frequency of 25 MHz in 100 Mbps mode and at 2.5 MHz in 10 Mbps mode. All MII receive signals that MAC receives are synchronous to MII_RX_CLK. The clock's input is required for all PHY interfaces.

And as I designed few RMII previously, I know that we need a clock to phy and MAC, Or a clock to phy and then from phy to MAC.

But in this design "S32K344 Evaluation Board for Mobile Robotics with 100BASE-T1 and Six CANFD" I found out that only "MII_RMII_TXCLK" is being used for RMII interface and it's from phy to MAC. But based on the Reference manual {If you select RMII mode, MII_RX_CLK (25 MHz or 2.5 MHz) must be derived from the RMII reference clock.} "MII_RX_CLK" clock also should be used.

So my questions are:

1. which one of above signals should be used for RMII interface?
2. what is the clock rate for them?

Thanks

[PavelL · Accepted solution]

Hello @rezrez ,

please refer to any S32K3's lwip example, where RMII works this way:

• PHY (like TJA1103) works in rev-RMII mode and generates TX clock 50MHz for MAC (e.g. S32K3)
• EMAC's RX clock input pin is not used
• Internal EMAC RX clock (as well as TX clock) is derived from TX clock input with divider 2 -> 25MHz

S32K344 RMII

Recently, RMII clocks been discussed in here Solved: S32K3_EMAC_RMII_why the RXCLK is 25Mhz - NXP Community  and here Solved: S32K388 RMII Reference Clock - NXP Community.

Best regards,

Pavel