S32K3_EMAC_RMII_why the RXCLK is 25Mhz

[wuxianlong]

Hi, NXP

When using the RMII mode of the EMAC module in S32K3x4, why is it necessary to configure MII_RX_CLK to 25MHz?

image.png

If configured to 50MHz, the data will be abnormal. Is there any more information about this description? I didn't find much description in the S32K3 RM manual. Why is MII_RX_CLK 25MHz in both MII and RMII modes? Is there any special operating principle?
image.png

Best Regards,
xianlong

[PavelL · Accepted solution]

Hello @wuxianlong ,

MII works with 4-bit data at 25MHz clock.

RMII works with 2-bit data at 50MHz clock. PHY (like TJA1103) usually works in rev-RMII mode, where PHY generates REF_CLK for MAC (S32K3/EMAC_MII_RMII_TX_CLK). RMII does not use external signal RX_CLK as can be seen on lwip examples.

The trick is that the EMAC processing data on CORE_CLK or AIPS_PLAT_CLK (depends on part number), which has higher frequency. EMAC is Synopsis IP and there are no more other information than in S32K3 RM.

Best regards,

Pavel

[wuxianlong]

Hi ,@PavelL 

Yes, I know that the RX clock pin does not need to be used. What I'm confused about is why it needs frequency division by two, and the configuration after frequency division by two is the same as MII.

The following screenshot is from Example Program lwip_baremetal_s32k344

image.png

Best Regards

xianlong

[PavelL]

Hello @wuxianlong ,

that's the condition defined by the IP provider. Notes in Table 550 can be reformulated this way:  both EMAC_TX_CLK and EMAC_RX_CLK should have 25 MHz independently of MII/RMII setup (for 100 Mbps), or 2.5 MHz (for 10 Mbps).

Best regards,

Pavel