PLL calculation for S32k312

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PLL calculation for S32k312

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9,713 Views
mogilipuri_harish
Contributor II

hello team,

 

i am using the S32K312 microchip in our design. can please help me to calculate the PLL output frequency. We are using 40 MHz external crystal oscillator. can you provide one example calculation? is it okay if you we are using 40 MHz crystal oscillator? 

please provide the clock calculator for S32K312.

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1 Solution
9,601 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@mogilipuri_harish

Apart from the data sheet, there is no more guidance document for clock configuration

As shown in the figure,the version RTD 2.0.1 and above have routines for S32K312

Senlent_0-1679275360762.png

 

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10 Replies
9,680 Views
mogilipuri_harish
Contributor II

hello senlent,

actually core clock frequency for S32k312 is 120Mhz.

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9,678 Views
Senlent
NXP TechSupport
NXP TechSupport

thanks for reminding

In S32K312, CORE_CLK=160Mhz can still run, but it is not recommended for customers to use this way, there will be unknown risks

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9,670 Views
mogilipuri_harish
Contributor II

here what are the variable values we can change??

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9,653 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi,

Didn't fully understand your question, do you mean which divider values can be changed?

Senlent_0-1679014916370.png

these parameters in the picture can be changed, you can view these clock tree configuration in S32 DS.

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9,639 Views
mogilipuri_harish
Contributor II

hi

 

Fxosc = 16MHz

PLL = (16/2)*60=480MHz

POSTDIV = 480/2 = 240MHz

PHIO = 240MHz/2 = 120MHz

CORE CLK = 120MHz/1=120MHz.

Can you please verify the PLL calculation for 120MHz? 

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2,824 Views
rekhak
Contributor I
Hi @mogilipuri_harish , were you able to resolve this issue. i am also dealing with same issue. i do have exactly same configuration , using MCAL 6.0.0 for S32K312.
facing error with "PLL ODIV2 = 2 " out of range
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9,629 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi,

for your reference,for example:

Senlent_0-1679045256458.png

PLL output frequency must be in range:640MHz~1,28GHz.

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9,626 Views
mogilipuri_harish
Contributor II

hi 

i am trying do this PLL clock calculation. can you given some notes how to do this calculation? like reference document. and i didn't find S32k312 example in tools, can you please share that it will be helpful to me.

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9,602 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@mogilipuri_harish

Apart from the data sheet, there is no more guidance document for clock configuration

As shown in the figure,the version RTD 2.0.1 and above have routines for S32K312

Senlent_0-1679275360762.png

 

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9,683 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@mogilipuri_harish

The FXOSC can be from 8MHz to40MHz,so the 40MHz crystal oscillator should be ok.

you can use "S32 Design Studio for S32 Platform" to set the clock tree.

for example:

Senlent_0-1678946272283.png

PS:The S32K312EVB we provide uses a 16MHz external crystal oscillator

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