PIT0 timer accuracy

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

PIT0 timer accuracy

383 Views
kamapat04
Contributor I

Hi,

I am working with the S32K311 microcontroller and have configured PIT0 to generate periodic interrupts every 1ms.
The system clock is derived from PLL0, configured to output 30MHz as PIT clock,

Accordingly, I have set the PIT0 load value (LDVAL) to 30000 as per the reference manual.
I am observing that the interrupt occurs approximately every 989–990 µs, resulting in a drift of about 1%.
Is this 1% deviation considered as normal behaviour or need to do some additional configuration?
Can you please let me know what is the accuracy of the PIT0 timer ?

 

Thanks,

Kamalesh

0 Kudos
Reply
1 Reply

357 Views
_Leo_
NXP TechSupport
NXP TechSupport

Thank you for your interest in our products and for contributing to our community.

A crystal-driven PLL locks both the phase and frequency to the reference crystal signal, thereby inheriting the crystal’s specified stability and accuracy, typically measured in parts per million (PPM). As a result, the frequency accuracy of the PLL output—expressed as a ±PPM deviation from the target output frequency—is effectively the same as that of the crystal reference. This is because the PLL maintains synchronization with the input signal in both phase and frequency.

Similarly, the resolution of timing modules such as PIT is determined by the accuracy of their reference clock source. Intermediate frequency dividers do not affect the overall accuracy in PPM, as they scale the frequency but not the relative timing precision.

I hope this information is helpful.

0 Kudos
Reply