Main reset domain (RD0) Mentioned in the STCU2 module

[luhaiou]

in file S32K3_SPD_BIST_UM.pdf,Mentioned "Main reset domain (RD0)",

Table 3-[1],S32K3xx Reference Manual,I didn't find a full explanation about "Main reset domain (RD0)"

I would like the NXP team to help explain what Main reset domain (RD0) means.

Looking forward to your reply, thank you very much.

[petervlna]

Hello,

Main reset domain is the reset state of the device for K3. S32K3 has just one.

So the more complex devices, has more reset domains, but this is not the case of S32K3.

Best regards,

Peter

[luhaiou]

Thanks for your reply

“Main reset domain is the reset state of the device for K3. S32K3 has just one”

I want to know What is the relationship between main reset and destructive reset and functional reset and POR?

[petervlna · Accepted solution]

Hello,

Not sure what do you mean by main reset. Looking at reference manual, it seems to me that main reset is term taken from devices that apply multiple reset domains. So its just a general term and here it will mean the reset domain, as here is only one.

But Reset generation module embed:

So there are only these in so called "main domain":

• Chip reset sequences
— POR
— Destructive reset
— Functional reset

Best regards,

Peter