MWCD2D16S VDD/V15 power up/down timing

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MWCD2D16S VDD/V15 power up/down timing

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Devin51
Contributor II

Hi NXP experts,

In our`s design,we use 1.5V from DCDC  as supply for VDD,and use a 3V3 LDO  as VDD supply.

What`s the requirements of MWCD2D16S VDD and V15 power up/down timing?

 

I can`t find the requirements of these in DS or RM,except vramp requirements:

企业微信截图_17580699335798.png

 

both vdd and v15 need rise up within 100V/ms~0.5V/min?

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi

I can't find the MWCD2D16S, and I'm not sure if the MWCD2D16S you're referring to is the MWCT2D16S.

In the S32K3 MCUs, there is not a power up/down sequence but the customer must respect the power-on ramp rate and the VREFH should always be equal to or less than VDD_HV_A +0.1.

Section 2.10.1 MCU Power Supply Ramp Rate in S32K3xx - Hardware Design Guidelines -- Rev_E2.pdf mentions the ramp rate of VDD_HV_A, VDD_HV_B and V15:

 

2.10.1 MCU Power Supply Ramp rate S32K3xx - Hardware Design Guidelines -- Rev_E2.png


Best Regards,
Robin
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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi

I can't find the MWCD2D16S, and I'm not sure if the MWCD2D16S you're referring to is the MWCT2D16S.

In the S32K3 MCUs, there is not a power up/down sequence but the customer must respect the power-on ramp rate and the VREFH should always be equal to or less than VDD_HV_A +0.1.

Section 2.10.1 MCU Power Supply Ramp Rate in S32K3xx - Hardware Design Guidelines -- Rev_E2.pdf mentions the ramp rate of VDD_HV_A, VDD_HV_B and V15:

 

2.10.1 MCU Power Supply Ramp rate S32K3xx - Hardware Design Guidelines -- Rev_E2.png


Best Regards,
Robin
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%3CLINGO-SUB%20id%3D%22lingo-sub-2170711%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3EMWCD2D16S%20VDD%2FV15%20power%20up%2Fdown%20timing%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2170711%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3EHi%20NXP%20experts%2C%3C%2FP%3E%3CP%3EIn%20our%60s%20design%2Cwe%20use%201.5V%20from%20DCDC%26nbsp%3B%20as%20supply%20for%20VDD%2Cand%20use%20a%203V3%20LDO%26nbsp%3B%20as%20VDD%20supply.%3C%2FP%3E%3CP%3EWhat%60s%20the%20requirements%20of%20MWCD2D16S%20VDD%20and%20V15%20power%20up%2Fdown%20timing%EF%BC%9F%3C%2FP%3E%3CBR%20%2F%3E%3CP%3EI%20can%60t%20find%20the%20requirements%20of%20these%20in%20DS%20or%20RM%2Cexcept%20vramp%20requirements%3A%3C%2FP%3E%3CP%3E%3CSPAN%20class%3D%22lia-inline-image-display-wrapper%20lia-image-align-left%22%20image-alt%3D%22%E4%BC%81%E4%B8%9A%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_17580699335798.png%22%20style%3D%22width%3A%20400px%3B%22%3E%3Cspan%20class%3D%22lia-inline-image-display-wrapper%22%20image-alt%3D%22%E4%BC%81%E4%B8%9A%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_17580699335798.png%22%20style%3D%22width%3A%20400px%3B%22%3E%3Cimg%20src%3D%22https%3A%2F%2Fcommunity.nxp.com%2Ft5%2Fimage%2Fserverpage%2Fimage-id%2F357204iCE1C2D9B61BAA770%2Fimage-size%2Fmedium%3Fv%3Dv2%26amp%3Bpx%3D400%22%20role%3D%22button%22%20title%3D%22%E4%BC%81%E4%B8%9A%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_17580699335798.png%22%20alt%3D%22%E4%BC%81%E4%B8%9A%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_17580699335798.png%22%20%2F%3E%3C%2Fspan%3E%3C%2FSPAN%3E%3C%2FP%3E%3CBR%20%2F%3E%3CP%3Eboth%20vdd%20and%20v15%20need%20rise%20up%20within%20100V%2Fms~0.5V%2Fmin%3F%3C%2FP%3E%3C%2FLINGO-BODY%3E%3CLINGO-SUB%20id%3D%22lingo-sub-2170807%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%20translate%3D%22no%22%3ERe%3A%20MWCD2D16S%20VDD%2FV15%20power%20up%2Fdown%20timing%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2170807%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3EHi%3C%2FP%3E%0A%3CP%3EI%20can't%20find%20the%20MWC%3CFONT%20color%3D%22%23FF0000%22%3E%3CSTRONG%3ED%3C%2FSTRONG%3E%3C%2FFONT%3E2D16S%2C%20and%20I'm%20not%20sure%20if%20the%20MWCD2D16S%20you're%20referring%20to%20is%20the%20MWC%3CFONT%20color%3D%22%23339966%22%3E%3CSTRONG%3ET%3C%2FSTRONG%3E%3C%2FFONT%3E2D16S.%3C%2FP%3E%0A%3CP%3EIn%20the%20S32K3%20MCUs%2C%20there%20is%20not%20a%20power%20up%2Fdown%20sequence%20but%20the%20customer%20must%20respect%20the%20power-on%20ramp%20rate%20and%20the%20%3CSTRONG%3EVREFH%3C%2FSTRONG%3E%20should%20always%20be%20equal%20to%20or%20less%20than%20VDD_HV_A%20%2B0.1.%3C%2FP%3E%0A%3CP%3ESection%20%3CSTRONG%3E%3CEM%3E2.10.1%20MCU%20Power%20Supply%20Ramp%20Rate%3C%2FEM%3E%3C%2FSTRONG%3E%20in%20%3CSTRONG%3ES32K3xx%20-%20Hardware%20Design%20Guidelines%20--%20Rev_E2.pdf%3C%2FSTRONG%3E%20mentions%20the%20ramp%20rate%20of%20%3CSTRONG%3EVDD_HV_A%3C%2FSTRONG%3E%2C%20%3CSTRONG%3EVDD_HV_B%3C%2FSTRONG%3E%20and%20%3CSTRONG%3EV15%3C%2FSTRONG%3E%3A%3C%2FP%3E%0A%3CBR%20%2F%3E%0A%3CP%3E%3CSPAN%20class%3D%22lia-inline-image-display-wrapper%20lia-image-align-inline%22%20image-alt%3D%222.10.1%20MCU%20Power%20Supply%20Ramp%20rate%20S32K3xx%20-%20Hardware%20Design%20Guidelines%20--%20Rev_E2.png%22%20style%3D%22width%3A%20834px%3B%22%3E%3Cspan%20class%3D%22lia-inline-image-display-wrapper%22%20image-alt%3D%222.10.1%20MCU%20Power%20Supply%20Ramp%20rate%20S32K3xx%20-%20Hardware%20Design%20Guidelines%20--%20Rev_E2.png%22%20style%3D%22width%3A%20834px%3B%22%3E%3Cimg%20src%3D%22https%3A%2F%2Fcommunity.nxp.com%2Ft5%2Fimage%2Fserverpage%2Fimage-id%2F357232i58E460876DFBF68C%2Fimage-size%2Flarge%3Fv%3Dv2%26amp%3Bpx%3D999%22%20role%3D%22button%22%20title%3D%222.10.1%20MCU%20Power%20Supply%20Ramp%20rate%20S32K3xx%20-%20Hardware%20Design%20Guidelines%20--%20Rev_E2.png%22%20alt%3D%222.10.1%20MCU%20Power%20Supply%20Ramp%20rate%20S32K3xx%20-%20Hardware%20Design%20Guidelines%20--%20Rev_E2.png%22%20%2F%3E%3C%2Fspan%3E%3C%2FSPAN%3E%3C%2FP%3E%0A%3CP%3E%3CBR%20%2F%3EBest%20Regards%2C%3CBR%20%2F%3ERobin%3CBR%20%2F%3E-------------------------------------------------------------------------------%3CBR%20%2F%3ENote%3A%3CBR%20%2F%3E-%20If%20this%20post%20answers%20your%20question%2C%20please%20click%20the%20%22ACCEPT%20AS%20SOLUTION%22%20button.%20Thank%20you!%3C%2FP%3E%0A%3CP%3E-%20We%20are%20following%20threads%20for%207%20weeks%20after%20the%20last%20post%2C%20later%20replies%20are%20ignored%3CBR%20%2F%3EPlease%20open%20a%20new%20thread%20and%20refer%20to%20the%20closed%20one%2C%20if%20you%20have%20a%20related%20question%20at%20a%20later%20point%20in%20time.%3CBR%20%2F%3E-------------------------------------------------------------------------------%3C%2FP%3E%3C%2FLINGO-BODY%3E