Interrupt handling in S32K116 using quick start guide startup file

[jayashreepasane]

Hello All,

I am using S32K116 micro controller with startup.s provided by quick start guide. On this I have a following question.

When I am in a interrupt service routine, say if there is a another interrupt occuring, I do not see that interrupt in pending interrupt list of NVIC. Also wanted to know if core interrupts are disabled when current interrupt is being served?

From .s file , I do not see any nesting of Interrupts handling.

attaching startup.s file. 

[danielmartynek]

Hello jayashreepasane,

The S32K1xx derivatives (ARM Cortex M0+ core) have four interrupt priority levels.

Depending on the priority levels of the interrupts, one interrupt can preempt another or become pending.
Please see the ARM®v6-M Architecture Reference Manual
B1.3.2 Exceptions
Priority levels, execution priority, exception entry, and execution preemption

BR, Daniel

[jayashreepasane]

Hello Daniel,

Thank you for the reply.

For example, I am generating an LPIT (low power time interrupt) every 1ms, at the 5th interrupt ( meaning here 5ms I call a function which takes more than 1ms), what happens to the next interrupt of same priority level interrupt here?

I do not see this interrupt in pending ISR list, thats why I added this question.

Regards,

Jayashree P

[danielmartynek]

Hello Jayashree,

When exactly do you clear the LPIT Interrupt flag?
You would need clear the flag before the LPIT interrupt is asserted again.

BR, Daniel

[jayashreepasane]

Hello Daniel,

First thing that I do in interrupt routine is to clear LPIT interrupt flag.

Thanks,

Jayashree P

[danielmartynek · Accepted solution]

Jayashree P,

If you clear the LPIT flag of the 5th interrupt before the 6th LPIT interrupt gets triggered, then, at the end of the 5th ISR, you should see NVIC_ISPR[20] == 1.

If not, please share your project.

Thank you,

Daniel

[jayashreepasane]

Hello Daniel,

Thank you for providing the input, Becasue LPIT was disabled in the debug mode, pending ISR was not seen. Now at the end of the 5th ISR I see there is a pending interrupt.

Thanks,

Jayashree P