Hi :
Currently, I try to implement lockstep function, and according to the following question on NXP community, I also get the same value.
https://community.nxp.com/t5/S32K/Detecting-S32K358-Lockstep-Pairs/m-p/2045711?utm_source=chatgpt.co...
My question is that how to test and check the lockstep status when system trigger core0 and core1 have something fault?
Thanks
BR, BillWen
已解决! 转到解答。
Hello,
According to the following picture, both SAF and SPD provide Bist and eMcem function, is there any different between SAF and SPD of BIST and eMcem?
SAF is extension of SPD. There is no difference in MIST and eMcem between them from SW point of view as far as I know.
Best regards,
Peter
Hi Peter:
Thanks for your reply.
Last question, how about SPD for testing BIST or eMCEM? According to the following picture, both SAF and SPD provide Bist and eMcem function, is there any different between SAF and SPD of BIST and eMcem? Our company need to consider about these solution for ISO26262 or others in the future. Do you have any suggestion? Thanks.
Thanks
BR, BillWen
Hello,
According to the following picture, both SAF and SPD provide Bist and eMcem function, is there any different between SAF and SPD of BIST and eMcem?
SAF is extension of SPD. There is no difference in MIST and eMcem between them from SW point of view as far as I know.
Best regards,
Peter
Hello,
Not sure if I understand your English correctly.
how to test and check the lockstep status when system trigger core0 and core1 have something fault?
Lock step status is reflected in DCM_GPR.DCMROF19.
If there is fault in system, it will logged in FCCU module NCF_S register.
Best regards,
Peter
Hello,
To test the lockstep functionality of K3 series, SAF software package sCheck for RCCU could be referred. RCCU is a hardware module for lockstep check while sCheck could inject error to RCCU using EIM.
Best regards,
Peter