How to switch clock source from FIRC to PLL_PHI0 for S32K3?

[vusal]

Hi,

I need to switch the clock source to PLL_PHI0 manually, meaning bare-metal, using registers. It looks like there are two ways to do this: Hardware and software. I tried setting up the hardware option; however, the status register (MUX_0_CSS[SELCTL]) still shows FIRC. MUX_0_CSC[SELCTL] shows 1000b (for PLL_PHI0) however, this is not reflected in the status register (MUX_0_CSS[SELCTL]).

Thanks for your help.

Vusal

[Robin_Shen]

Hi Vusal,

Please refer to the attached project: clock_test.zip
Hope it helps.

Best Regards,
Robin
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[vusal]

Hi Robin,

Thank you for your response.

I moved the following code (please see below) into my project and tried building, however I got 010b in SWTRG bits in the Clock Mux 0 Select Status Register, which indicates the clock I am trying to switch is not active?

"010b - Switch after the request failed because of an inactive target clock and the current clock is FIRC."

If so, how do I activate PLL?

Thanks!

Best,
Vusal

This is the code I moved into my project:

#define CLOCK_MuxInit_(mux, src, div) \
do{ \
while((MC_CGM->MUX_##mux##_CSS & MC_CGM_MUX_##mux##_CSS_SWIP_MASK) != 0) \
{ \
} \
if(div == 0) \
{ \
MC_CGM->MUX_##mux##_DC_0 = 0ul; \
} \
else \
{ \
MC_CGM->MUX_##mux##_CSC = MC_CGM_MUX_##mux##_CSC_SELCTL(src); \
MC_CGM->MUX_##mux##_DC_0 = MC_CGM_MUX_##mux##_DC_0_DIV(div - 1); \
MC_CGM->MUX_##mux##_DC_0 |= MC_CGM_MUX_##mux##_DC_0_DE_MASK; \
while((MC_CGM->MUX_##mux##_DIV_UPD_STAT & MC_CGM_MUX_##mux##_DIV_UPD_STAT_DIV_STAT_MASK) != 0) \
{ \
} \
MC_CGM->MUX_##mux##_CSC |= MC_CGM_MUX_##mux##_CSC_CLK_SW_MASK; \
while((MC_CGM->MUX_##mux##_CSS & MC_CGM_MUX_##mux##_CSS_CLK_SW_MASK) == 0) \
{ \
} \
while((MC_CGM->MUX_##mux##_CSS & MC_CGM_MUX_1_CSS_SWIP_MASK) != 0) \
{ \
} \
} \
}while(0)

[Robin_Shen · Accepted solution]

Please refer to the CLOCK_Init function in clock_test project.

[vusal]

Hi Robin,

I incorporated the CLOCK_Init into my project and it worked. I can see on the status register (MUX_0_CSS) that my clock source switched to the PLL_PHI0_CLK.

Thank you very much for your help!

Best,
Vusal

[vusal]

Thank you, Robin. This is helpful. I'll take a look.